1*7ac6a76cSjason-ch chen /*
2*7ac6a76cSjason-ch chen * Copyright (c) 2022, MediaTek Inc. All rights reserved.
3*7ac6a76cSjason-ch chen *
4*7ac6a76cSjason-ch chen * SPDX-License-Identifier: BSD-3-Clause
5*7ac6a76cSjason-ch chen */
6*7ac6a76cSjason-ch chen
7*7ac6a76cSjason-ch chen #include <stddef.h>
8*7ac6a76cSjason-ch chen #include <string.h>
9*7ac6a76cSjason-ch chen #include <common/debug.h>
10*7ac6a76cSjason-ch chen #include <lib/bakery_lock.h>
11*7ac6a76cSjason-ch chen #include <lib/mmio.h>
12*7ac6a76cSjason-ch chen #include <mt_lp_rm.h>
13*7ac6a76cSjason-ch chen #include <mt_spm.h>
14*7ac6a76cSjason-ch chen #include <mt_spm_cond.h>
15*7ac6a76cSjason-ch chen #include <mt_spm_conservation.h>
16*7ac6a76cSjason-ch chen #include <mt_spm_constraint.h>
17*7ac6a76cSjason-ch chen #include "mt_spm_extern.h"
18*7ac6a76cSjason-ch chen #include <mt_spm_idle.h>
19*7ac6a76cSjason-ch chen #include <mt_spm_internal.h>
20*7ac6a76cSjason-ch chen #include <mt_spm_pmic_wrap.h>
21*7ac6a76cSjason-ch chen #include <mt_spm_rc_internal.h>
22*7ac6a76cSjason-ch chen #include <mt_spm_reg.h>
23*7ac6a76cSjason-ch chen #include <mt_spm_resource_req.h>
24*7ac6a76cSjason-ch chen #include <mt_spm_suspend.h>
25*7ac6a76cSjason-ch chen #include <mtk_plat_common.h>
26*7ac6a76cSjason-ch chen #include <plat_mtk_lpm.h>
27*7ac6a76cSjason-ch chen #include <plat_pm.h>
28*7ac6a76cSjason-ch chen #include <platform_def.h>
29*7ac6a76cSjason-ch chen #include <sleep_def.h>
30*7ac6a76cSjason-ch chen
31*7ac6a76cSjason-ch chen #ifdef MT_SPM_USING_BAKERY_LOCK
32*7ac6a76cSjason-ch chen DEFINE_BAKERY_LOCK(spm_lock);
33*7ac6a76cSjason-ch chen #define plat_spm_lock_init() bakery_lock_init(&spm_lock)
34*7ac6a76cSjason-ch chen #else
35*7ac6a76cSjason-ch chen spinlock_t spm_lock;
36*7ac6a76cSjason-ch chen #define plat_spm_lock_init()
37*7ac6a76cSjason-ch chen #endif
38*7ac6a76cSjason-ch chen
39*7ac6a76cSjason-ch chen /* CLK_SCP_CFG_0 */
40*7ac6a76cSjason-ch chen #define CLK_SCP_CFG_0 (TOPCKGEN_BASE + 0x200)
41*7ac6a76cSjason-ch chen #define SPM_CK_CONTROL_EN (0x3FF)
42*7ac6a76cSjason-ch chen
43*7ac6a76cSjason-ch chen /* CLK_SCP_CFG_1 */
44*7ac6a76cSjason-ch chen #define CLK_SCP_CFG_1 (TOPCKGEN_BASE + 0x210)
45*7ac6a76cSjason-ch chen #define CLK_SCP_CFG_1_MASK (0x100C)
46*7ac6a76cSjason-ch chen #define CLK_SCP_CFG_1_SPM (0x3)
47*7ac6a76cSjason-ch chen
48*7ac6a76cSjason-ch chen #define MT_SPM_EX_OP_TIME_CHECK BIT(10)
49*7ac6a76cSjason-ch chen
50*7ac6a76cSjason-ch chen struct mt_resource_constraint plat_constraint_bus26m = {
51*7ac6a76cSjason-ch chen .is_valid = spm_is_valid_rc_bus26m,
52*7ac6a76cSjason-ch chen .update = spm_update_rc_bus26m,
53*7ac6a76cSjason-ch chen .allow = spm_allow_rc_bus26m,
54*7ac6a76cSjason-ch chen .run = spm_run_rc_bus26m,
55*7ac6a76cSjason-ch chen .reset = spm_reset_rc_bus26m,
56*7ac6a76cSjason-ch chen };
57*7ac6a76cSjason-ch chen
58*7ac6a76cSjason-ch chen struct mt_resource_constraint plat_constraint_syspll = {
59*7ac6a76cSjason-ch chen .is_valid = spm_is_valid_rc_syspll,
60*7ac6a76cSjason-ch chen .update = spm_update_rc_syspll,
61*7ac6a76cSjason-ch chen .allow = spm_allow_rc_syspll,
62*7ac6a76cSjason-ch chen .run = spm_run_rc_syspll,
63*7ac6a76cSjason-ch chen .reset = spm_reset_rc_syspll,
64*7ac6a76cSjason-ch chen };
65*7ac6a76cSjason-ch chen
66*7ac6a76cSjason-ch chen struct mt_resource_constraint plat_constraint_dram = {
67*7ac6a76cSjason-ch chen .is_valid = spm_is_valid_rc_dram,
68*7ac6a76cSjason-ch chen .update = spm_update_rc_dram,
69*7ac6a76cSjason-ch chen .allow = spm_allow_rc_dram,
70*7ac6a76cSjason-ch chen .run = spm_run_rc_dram,
71*7ac6a76cSjason-ch chen .reset = spm_reset_rc_dram,
72*7ac6a76cSjason-ch chen };
73*7ac6a76cSjason-ch chen
74*7ac6a76cSjason-ch chen /* Maybe remove when the spm won't cpu power control aymore */
75*7ac6a76cSjason-ch chen struct mt_resource_constraint plat_constraint_cpu = {
76*7ac6a76cSjason-ch chen .is_valid = spm_is_valid_rc_cpu_buck_ldo,
77*7ac6a76cSjason-ch chen .update = NULL,
78*7ac6a76cSjason-ch chen .allow = spm_allow_rc_cpu_buck_ldo,
79*7ac6a76cSjason-ch chen .run = spm_run_rc_cpu_buck_ldo,
80*7ac6a76cSjason-ch chen .reset = spm_reset_rc_cpu_buck_ldo,
81*7ac6a76cSjason-ch chen };
82*7ac6a76cSjason-ch chen
83*7ac6a76cSjason-ch chen struct mt_resource_constraint *plat_constraints[] = {
84*7ac6a76cSjason-ch chen &plat_constraint_bus26m,
85*7ac6a76cSjason-ch chen &plat_constraint_syspll,
86*7ac6a76cSjason-ch chen &plat_constraint_dram,
87*7ac6a76cSjason-ch chen &plat_constraint_cpu,
88*7ac6a76cSjason-ch chen NULL,
89*7ac6a76cSjason-ch chen };
90*7ac6a76cSjason-ch chen
91*7ac6a76cSjason-ch chen struct mt_resource_manager plat_mt8186_rm = {
92*7ac6a76cSjason-ch chen .update = mt_spm_cond_update,
93*7ac6a76cSjason-ch chen .consts = plat_constraints,
94*7ac6a76cSjason-ch chen };
95*7ac6a76cSjason-ch chen
spm_boot_init(void)96*7ac6a76cSjason-ch chen void spm_boot_init(void)
97*7ac6a76cSjason-ch chen {
98*7ac6a76cSjason-ch chen NOTICE("MT8186 %s\n", __func__);
99*7ac6a76cSjason-ch chen
100*7ac6a76cSjason-ch chen /* switch ck_off/axi_26m control to SPM */
101*7ac6a76cSjason-ch chen mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_CONTROL_EN);
102*7ac6a76cSjason-ch chen mmio_clrsetbits_32(CLK_SCP_CFG_1, CLK_SCP_CFG_1_MASK, CLK_SCP_CFG_1_SPM);
103*7ac6a76cSjason-ch chen
104*7ac6a76cSjason-ch chen plat_spm_lock_init();
105*7ac6a76cSjason-ch chen mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE);
106*7ac6a76cSjason-ch chen mt_lp_rm_register(&plat_mt8186_rm);
107*7ac6a76cSjason-ch chen mt_spm_idle_generic_init();
108*7ac6a76cSjason-ch chen mt_spm_suspend_init();
109*7ac6a76cSjason-ch chen spm_extern_initialize();
110*7ac6a76cSjason-ch chen }
111