1*6e5d76baSYuchen Huang /* 2*6e5d76baSYuchen Huang * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3*6e5d76baSYuchen Huang * 4*6e5d76baSYuchen Huang * SPDX-License-Identifier: BSD-3-Clause 5*6e5d76baSYuchen Huang */ 6*6e5d76baSYuchen Huang 7*6e5d76baSYuchen Huang #ifndef RTC_H 8*6e5d76baSYuchen Huang #define RTC_H 9*6e5d76baSYuchen Huang 10*6e5d76baSYuchen Huang #define PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK (1U) 11*6e5d76baSYuchen Huang #define PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT (1U) 12*6e5d76baSYuchen Huang #define PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK (1U) 13*6e5d76baSYuchen Huang #define PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT (3U) 14*6e5d76baSYuchen Huang #define PMIC_RG_RTC_EOSC32_CK_PDN_MASK (1U) 15*6e5d76baSYuchen Huang #define PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT (2U) 16*6e5d76baSYuchen Huang #define PMIC_RG_EOSC_CALI_TD_MASK (7U) 17*6e5d76baSYuchen Huang #define PMIC_RG_EOSC_CALI_TD_SHIFT (5U) 18*6e5d76baSYuchen Huang #define PMIC_RG_XO_EN32K_MAN_MASK (1U) 19*6e5d76baSYuchen Huang #define PMIC_RG_XO_EN32K_MAN_SHIFT (0U) 20*6e5d76baSYuchen Huang 21*6e5d76baSYuchen Huang /* RTC registers */ 22*6e5d76baSYuchen Huang enum { 23*6e5d76baSYuchen Huang RTC_BBPU = 0x0588, 24*6e5d76baSYuchen Huang RTC_IRQ_STA = 0x058A, 25*6e5d76baSYuchen Huang RTC_IRQ_EN = 0x058C, 26*6e5d76baSYuchen Huang RTC_CII_EN = 0x058E 27*6e5d76baSYuchen Huang }; 28*6e5d76baSYuchen Huang 29*6e5d76baSYuchen Huang enum { 30*6e5d76baSYuchen Huang RTC_AL_SEC = 0x05A0, 31*6e5d76baSYuchen Huang RTC_AL_MIN = 0x05A2, 32*6e5d76baSYuchen Huang RTC_AL_HOU = 0x05A4, 33*6e5d76baSYuchen Huang RTC_AL_DOM = 0x05A6, 34*6e5d76baSYuchen Huang RTC_AL_DOW = 0x05A8, 35*6e5d76baSYuchen Huang RTC_AL_MTH = 0x05AA, 36*6e5d76baSYuchen Huang RTC_AL_YEA = 0x05AC, 37*6e5d76baSYuchen Huang RTC_AL_MASK = 0x0590 38*6e5d76baSYuchen Huang }; 39*6e5d76baSYuchen Huang 40*6e5d76baSYuchen Huang enum { 41*6e5d76baSYuchen Huang RTC_OSC32CON = 0x05AE, 42*6e5d76baSYuchen Huang RTC_CON = 0x05C4, 43*6e5d76baSYuchen Huang RTC_WRTGR = 0x05C2 44*6e5d76baSYuchen Huang }; 45*6e5d76baSYuchen Huang 46*6e5d76baSYuchen Huang enum { 47*6e5d76baSYuchen Huang RTC_PDN1 = 0x05B4, 48*6e5d76baSYuchen Huang RTC_PDN2 = 0x05B6, 49*6e5d76baSYuchen Huang RTC_SPAR0 = 0x05B8, 50*6e5d76baSYuchen Huang RTC_SPAR1 = 0x05BA, 51*6e5d76baSYuchen Huang RTC_PROT = 0x05BC, 52*6e5d76baSYuchen Huang RTC_DIFF = 0x05BE, 53*6e5d76baSYuchen Huang RTC_CALI = 0x05C0 54*6e5d76baSYuchen Huang }; 55*6e5d76baSYuchen Huang 56*6e5d76baSYuchen Huang enum { 57*6e5d76baSYuchen Huang RTC_OSC32CON_UNLOCK1 = 0x1A57, 58*6e5d76baSYuchen Huang RTC_OSC32CON_UNLOCK2 = 0x2B68 59*6e5d76baSYuchen Huang }; 60*6e5d76baSYuchen Huang 61*6e5d76baSYuchen Huang enum { 62*6e5d76baSYuchen Huang RTC_PROT_UNLOCK1 = 0x586A, 63*6e5d76baSYuchen Huang RTC_PROT_UNLOCK2 = 0x9136 64*6e5d76baSYuchen Huang }; 65*6e5d76baSYuchen Huang 66*6e5d76baSYuchen Huang enum { 67*6e5d76baSYuchen Huang RTC_BBPU_PWREN = 1U << 0, 68*6e5d76baSYuchen Huang RTC_BBPU_CLR = 1U << 1, 69*6e5d76baSYuchen Huang RTC_BBPU_INIT = 1U << 2, 70*6e5d76baSYuchen Huang RTC_BBPU_AUTO = 1U << 3, 71*6e5d76baSYuchen Huang RTC_BBPU_CLRPKY = 1U << 4, 72*6e5d76baSYuchen Huang RTC_BBPU_RELOAD = 1U << 5, 73*6e5d76baSYuchen Huang RTC_BBPU_CBUSY = 1U << 6 74*6e5d76baSYuchen Huang }; 75*6e5d76baSYuchen Huang 76*6e5d76baSYuchen Huang enum { 77*6e5d76baSYuchen Huang RTC_AL_MASK_SEC = 1U << 0, 78*6e5d76baSYuchen Huang RTC_AL_MASK_MIN = 1U << 1, 79*6e5d76baSYuchen Huang RTC_AL_MASK_HOU = 1U << 2, 80*6e5d76baSYuchen Huang RTC_AL_MASK_DOM = 1U << 3, 81*6e5d76baSYuchen Huang RTC_AL_MASK_DOW = 1U << 4, 82*6e5d76baSYuchen Huang RTC_AL_MASK_MTH = 1U << 5, 83*6e5d76baSYuchen Huang RTC_AL_MASK_YEA = 1U << 6 84*6e5d76baSYuchen Huang }; 85*6e5d76baSYuchen Huang 86*6e5d76baSYuchen Huang enum { 87*6e5d76baSYuchen Huang RTC_BBPU_AUTO_PDN_SEL = 1U << 6, 88*6e5d76baSYuchen Huang RTC_BBPU_2SEC_CK_SEL = 1U << 7, 89*6e5d76baSYuchen Huang RTC_BBPU_2SEC_EN = 1U << 8, 90*6e5d76baSYuchen Huang RTC_BBPU_2SEC_MODE = 0x3 << 9, 91*6e5d76baSYuchen Huang RTC_BBPU_2SEC_STAT_CLEAR = 1U << 11, 92*6e5d76baSYuchen Huang RTC_BBPU_2SEC_STAT_STA = 1U << 12 93*6e5d76baSYuchen Huang }; 94*6e5d76baSYuchen Huang 95*6e5d76baSYuchen Huang enum { 96*6e5d76baSYuchen Huang RTC_BBPU_KEY = 0x43 << 8 97*6e5d76baSYuchen Huang }; 98*6e5d76baSYuchen Huang 99*6e5d76baSYuchen Huang enum { 100*6e5d76baSYuchen Huang RTC_EMBCK_SRC_SEL = 1 << 8, 101*6e5d76baSYuchen Huang RTC_EMBCK_SEL_MODE = 3 << 6, 102*6e5d76baSYuchen Huang RTC_XOSC32_ENB = 1 << 5, 103*6e5d76baSYuchen Huang RTC_REG_XOSC32_ENB = 1 << 15 104*6e5d76baSYuchen Huang }; 105*6e5d76baSYuchen Huang 106*6e5d76baSYuchen Huang enum { 107*6e5d76baSYuchen Huang RTC_K_EOSC_RSV_0 = 1 << 8, 108*6e5d76baSYuchen Huang RTC_K_EOSC_RSV_1 = 1 << 9, 109*6e5d76baSYuchen Huang RTC_K_EOSC_RSV_2 = 1 << 10 110*6e5d76baSYuchen Huang }; 111*6e5d76baSYuchen Huang 112*6e5d76baSYuchen Huang /* PMIC TOP Register Definition */ 113*6e5d76baSYuchen Huang enum { 114*6e5d76baSYuchen Huang PMIC_RG_TOP_CON = 0x001E, 115*6e5d76baSYuchen Huang PMIC_RG_TOP_CKPDN_CON1 = 0x0112, 116*6e5d76baSYuchen Huang PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114, 117*6e5d76baSYuchen Huang PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116, 118*6e5d76baSYuchen Huang PMIC_RG_TOP_CKSEL_CON0 = 0x0118, 119*6e5d76baSYuchen Huang PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A, 120*6e5d76baSYuchen Huang PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C 121*6e5d76baSYuchen Huang }; 122*6e5d76baSYuchen Huang 123*6e5d76baSYuchen Huang /* PMIC SCK Register Definition */ 124*6e5d76baSYuchen Huang enum { 125*6e5d76baSYuchen Huang PMIC_RG_SCK_TOP_CKPDN_CON0 = 0x051A, 126*6e5d76baSYuchen Huang PMIC_RG_SCK_TOP_CKPDN_CON0_SET = 0x051C, 127*6e5d76baSYuchen Huang PMIC_RG_SCK_TOP_CKPDN_CON0_CLR = 0x051E, 128*6e5d76baSYuchen Huang PMIC_RG_EOSC_CALI_CON0 = 0x540 129*6e5d76baSYuchen Huang }; 130*6e5d76baSYuchen Huang 131*6e5d76baSYuchen Huang /* PMIC DCXO Register Definition */ 132*6e5d76baSYuchen Huang enum { 133*6e5d76baSYuchen Huang PMIC_RG_DCXO_CW00 = 0x0788, 134*6e5d76baSYuchen Huang PMIC_RG_DCXO_CW02 = 0x0790 135*6e5d76baSYuchen Huang }; 136*6e5d76baSYuchen Huang 137*6e5d76baSYuchen Huang /* external API */ 138*6e5d76baSYuchen Huang uint16_t RTC_Read(uint32_t addr); 139*6e5d76baSYuchen Huang void RTC_Write(uint32_t addr, uint16_t data); 140*6e5d76baSYuchen Huang int32_t rtc_busy_wait(void); 141*6e5d76baSYuchen Huang int32_t RTC_Write_Trigger(void); 142*6e5d76baSYuchen Huang int32_t Writeif_unlock(void); 143*6e5d76baSYuchen Huang void rtc_power_off_sequence(void); 144*6e5d76baSYuchen Huang 145*6e5d76baSYuchen Huang #endif /* RTC_H */ 146