1 /* 2 * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <string.h> 8 9 #include <drivers/delay_timer.h> 10 11 #include <mt_cpu_pm_cpc.h> 12 #include <mt_timer.h> 13 14 struct mtk_cpc_dev { 15 int auto_off; 16 unsigned int auto_thres_tick; 17 }; 18 19 static struct mtk_cpc_dev cpc; 20 21 static int mtk_cpc_last_core_prot(uint32_t prot_req, 22 uint32_t resp_reg, uint32_t resp_ofs) 23 { 24 uint32_t sta, retry; 25 26 retry = 0U; 27 28 while (retry++ < RETRY_CNT_MAX) { 29 30 mmio_write_32(CPC_MCUSYS_LAST_CORE_REQ, prot_req); 31 32 udelay(1U); 33 34 sta = (mmio_read_32(resp_reg) >> resp_ofs) & CPC_PROT_RESP_MASK; 35 36 if (sta == PROT_SUCCESS) { 37 return CPC_SUCCESS; 38 } else if (sta == PROT_GIVEUP) { 39 return CPC_ERR_FAIL; 40 } 41 } 42 43 return CPC_ERR_TIMEOUT; 44 } 45 46 int mtk_cpu_pm_mcusys_prot_aquire(void) 47 { 48 return mtk_cpc_last_core_prot( 49 MCUSYS_PROT_SET, 50 CPC_MCUSYS_LAST_CORE_RESP, 51 MCUSYS_RESP_OFS); 52 } 53 54 void mtk_cpu_pm_mcusys_prot_release(void) 55 { 56 mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, MCUSYS_PROT_CLR); 57 } 58 59 int mtk_cpu_pm_cluster_prot_aquire(unsigned int cluster) 60 { 61 return mtk_cpc_last_core_prot( 62 CPUSYS_PROT_SET, 63 CPC_MCUSYS_MP_LAST_CORE_RESP, 64 CPUSYS_RESP_OFS); 65 } 66 67 void mtk_cpu_pm_cluster_prot_release(unsigned int cluster) 68 { 69 mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, CPUSYS_PROT_CLR); 70 } 71 72 static void mtk_cpc_cluster_cnt_backup(void) 73 { 74 uint32_t backup_cnt; 75 uint32_t curr_cnt; 76 uint32_t cnt_mask = GENMASK(14, 0); 77 uint32_t clr_mask = GENMASK(1, 0); 78 79 /* Single Cluster */ 80 backup_cnt = mmio_read_32(CPC_CLUSTER_CNT_BACKUP); 81 curr_cnt = mmio_read_32(CPC_MCUSYS_CLUSTER_COUNTER); 82 83 /* Get off count if dormant count is 0 */ 84 if ((curr_cnt & cnt_mask) == 0U) { 85 curr_cnt = (curr_cnt >> 16) & cnt_mask; 86 } else { 87 curr_cnt = curr_cnt & cnt_mask; 88 } 89 90 mmio_write_32(CPC_CLUSTER_CNT_BACKUP, backup_cnt + curr_cnt); 91 mmio_write_32(CPC_MCUSYS_CLUSTER_COUNTER_CLR, clr_mask); 92 } 93 94 static inline void mtk_cpc_mcusys_off_en(void) 95 { 96 mmio_write_32(CPC_MCUSYS_PWR_CTRL, 1U); 97 } 98 99 static inline void mtk_cpc_mcusys_off_dis(void) 100 { 101 mmio_write_32(CPC_MCUSYS_PWR_CTRL, 0U); 102 } 103 104 void mtk_cpc_mcusys_off_reflect(void) 105 { 106 mtk_cpc_mcusys_off_dis(); 107 mtk_cpu_pm_mcusys_prot_release(); 108 } 109 110 int mtk_cpc_mcusys_off_prepare(void) 111 { 112 if (mtk_cpu_pm_mcusys_prot_aquire() != CPC_SUCCESS) { 113 return CPC_ERR_FAIL; 114 } 115 116 mtk_cpc_cluster_cnt_backup(); 117 mtk_cpc_mcusys_off_en(); 118 119 return CPC_SUCCESS; 120 } 121 122 void mtk_cpc_core_on_hint_set(unsigned int cpu) 123 { 124 mmio_write_32(CPC_MCUSYS_CPU_ON_SW_HINT_SET, BIT(cpu)); 125 } 126 127 void mtk_cpc_core_on_hint_clr(unsigned int cpu) 128 { 129 mmio_write_32(CPC_MCUSYS_CPU_ON_SW_HINT_CLR, BIT(cpu)); 130 } 131 132 static void mtk_cpc_dump_timestamp(void) 133 { 134 uint32_t id; 135 136 for (id = 0U; id < CPC_TRACE_ID_NUM; id++) { 137 mmio_write_32(CPC_MCUSYS_TRACE_SEL, id); 138 139 memcpy((void *)(uintptr_t)CPC_TRACE_SRAM(id), 140 (const void *)(uintptr_t)CPC_MCUSYS_TRACE_DATA, 141 CPC_TRACE_SIZE); 142 } 143 } 144 145 void mtk_cpc_time_sync(void) 146 { 147 uint64_t kt; 148 uint32_t systime_l, systime_h; 149 150 kt = sched_clock(); 151 systime_l = mmio_read_32(CNTSYS_L_REG); 152 systime_h = mmio_read_32(CNTSYS_H_REG); 153 154 /* sync kernel timer to cpc */ 155 mmio_write_32(CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE, (uint32_t)kt); 156 mmio_write_32(CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE, (uint32_t)(kt >> 32)); 157 /* sync system timer to cpc */ 158 mmio_write_32(CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE, systime_l); 159 mmio_write_32(CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE, systime_h); 160 } 161 162 static void mtk_cpc_config(uint32_t cfg, uint32_t data) 163 { 164 uint32_t val; 165 uint32_t reg = 0U; 166 167 switch (cfg) { 168 case CPC_SMC_CONFIG_PROF: 169 reg = CPC_MCUSYS_CPC_DBG_SETTING; 170 val = mmio_read_32(reg); 171 val = (data != 0U) ? (val | CPC_PROF_EN) : (val & ~CPC_PROF_EN); 172 break; 173 case CPC_SMC_CONFIG_AUTO_OFF: 174 reg = CPC_MCUSYS_CPC_FLOW_CTRL_CFG; 175 val = mmio_read_32(reg); 176 if (data != 0U) { 177 val |= CPC_AUTO_OFF_EN; 178 cpc.auto_off = 1; 179 } else { 180 val &= ~CPC_AUTO_OFF_EN; 181 cpc.auto_off = 0; 182 } 183 break; 184 case CPC_SMC_CONFIG_AUTO_OFF_THRES: 185 reg = CPC_MCUSYS_CPC_OFF_THRES; 186 cpc.auto_thres_tick = us_to_ticks(data); 187 val = cpc.auto_thres_tick; 188 break; 189 case CPC_SMC_CONFIG_CNT_CLR: 190 reg = CPC_MCUSYS_CLUSTER_COUNTER_CLR; 191 val = GENMASK(1, 0); /* clr_mask */ 192 break; 193 case CPC_SMC_CONFIG_TIME_SYNC: 194 mtk_cpc_time_sync(); 195 break; 196 default: 197 break; 198 } 199 200 if (reg != 0U) { 201 mmio_write_32(reg, val); 202 } 203 } 204 205 static uint32_t mtk_cpc_read_config(uint32_t cfg) 206 { 207 uint32_t res = 0U; 208 209 switch (cfg) { 210 case CPC_SMC_CONFIG_PROF: 211 res = (mmio_read_32(CPC_MCUSYS_CPC_DBG_SETTING) & CPC_PROF_EN) ? 212 1U : 0U; 213 break; 214 case CPC_SMC_CONFIG_AUTO_OFF: 215 res = cpc.auto_off; 216 break; 217 case CPC_SMC_CONFIG_AUTO_OFF_THRES: 218 res = ticks_to_us(cpc.auto_thres_tick); 219 break; 220 case CPC_SMC_CONFIG_CNT_CLR: 221 break; 222 default: 223 break; 224 } 225 226 return res; 227 } 228 229 uint64_t mtk_cpc_handler(uint64_t act, uint64_t arg1, uint64_t arg2) 230 { 231 uint64_t res = 0ULL; 232 233 switch (act) { 234 case CPC_SMC_EVENT_DUMP_TRACE_DATA: 235 mtk_cpc_dump_timestamp(); 236 break; 237 case CPC_SMC_EVENT_GIC_DPG_SET: 238 /* isolated_status = x2; */ 239 break; 240 case CPC_SMC_EVENT_CPC_CONFIG: 241 mtk_cpc_config((uint32_t)arg1, (uint32_t)arg2); 242 break; 243 case CPC_SMC_EVENT_READ_CONFIG: 244 res = mtk_cpc_read_config((uint32_t)arg1); 245 break; 246 default: 247 break; 248 } 249 250 return res; 251 } 252 253 void mtk_cpc_init(void) 254 { 255 mmio_write_32(CPC_MCUSYS_CPC_DBG_SETTING, 256 mmio_read_32(CPC_MCUSYS_CPC_DBG_SETTING) 257 | CPC_DBG_EN 258 | CPC_CALC_EN); 259 260 cpc.auto_off = 1; 261 cpc.auto_thres_tick = us_to_ticks(8000); 262 263 mmio_write_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG, 264 mmio_read_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG) 265 | CPC_OFF_PRE_EN 266 | (cpc.auto_off ? CPC_AUTO_OFF_EN : 0U)); 267 268 mmio_write_32(CPC_MCUSYS_CPC_OFF_THRES, cpc.auto_thres_tick); 269 } 270