1 /* 2 * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <common/debug.h> 9 #include <lib/mmio.h> 10 #include <mtk_sip_svc.h> 11 #include <plat_dfd.h> 12 13 static bool dfd_enabled; 14 static uint64_t dfd_base_addr; 15 static uint64_t dfd_chain_length; 16 static uint64_t dfd_cache_dump; 17 18 static void dfd_setup(uint64_t base_addr, uint64_t chain_length, 19 uint64_t cache_dump) 20 { 21 mmio_write_32(MCUSYS_DFD_MAP, base_addr >> 24); 22 mmio_write_32(WDT_DEBUG_CTL, WDT_DEBUG_CTL_VAL_0); 23 24 sync_writel(DFD_INTERNAL_CTL, (BIT(0) | BIT(2))); 25 26 mmio_setbits_32(DFD_INTERNAL_CTL, BIT(13)); 27 mmio_setbits_32(DFD_INTERNAL_CTL, BIT(3)); 28 mmio_setbits_32(DFD_INTERNAL_CTL, (BIT(19) | BIT(20))); 29 mmio_write_32(DFD_INTERNAL_PWR_ON, (BIT(0) | BIT(1) | BIT(3))); 30 mmio_write_32(DFD_CHAIN_LENGTH0, chain_length); 31 mmio_write_32(DFD_INTERNAL_SHIFT_CLK_RATIO, 0); 32 mmio_write_32(DFD_INTERNAL_TEST_SO_0, DFD_INTERNAL_TEST_SO_0_VAL); 33 mmio_write_32(DFD_INTERNAL_NUM_OF_TEST_SO_GROUP, 1); 34 35 mmio_write_32(DFD_TEST_SI_0, DFD_TEST_SI_0_VAL); 36 mmio_write_32(DFD_TEST_SI_1, DFD_TEST_SI_1_VAL); 37 38 sync_writel(DFD_V30_CTL, 1); 39 40 mmio_write_32(DFD_V30_BASE_ADDR, (base_addr & 0xFFF00000)); 41 42 /* setup global variables for suspend and resume */ 43 dfd_enabled = true; 44 dfd_base_addr = base_addr; 45 dfd_chain_length = chain_length; 46 dfd_cache_dump = cache_dump; 47 48 if ((cache_dump & DFD_CACHE_DUMP_ENABLE) != 0UL) { 49 mmio_write_32(WDT_DEBUG_CTL, WDT_DEBUG_CTL_VAL_1); 50 sync_writel(DFD_V35_ENALBE, 1); 51 sync_writel(DFD_V35_TAP_NUMBER, DFD_V35_TAP_NUMBER_VAL); 52 sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL); 53 sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL); 54 55 if (cache_dump & DFD_PARITY_ERR_TRIGGER) { 56 sync_writel(DFD_HW_TRIGGER_MASK, DFD_HW_TRIGGER_MASK_VAL); 57 mmio_setbits_32(DFD_INTERNAL_CTL, BIT(4)); 58 } 59 } 60 dsbsy(); 61 } 62 63 void dfd_resume(void) 64 { 65 if (dfd_enabled == true) { 66 dfd_setup(dfd_base_addr, dfd_chain_length, dfd_cache_dump); 67 } 68 } 69 70 uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1, 71 uint64_t arg2, uint64_t arg3) 72 { 73 uint64_t ret = 0L; 74 75 switch (arg0) { 76 case PLAT_MTK_DFD_SETUP_MAGIC: 77 INFO("[%s] DFD setup call from kernel\n", __func__); 78 dfd_setup(arg1, arg2, arg3); 79 break; 80 case PLAT_MTK_DFD_READ_MAGIC: 81 /* only allow to access DFD register base + 0x200 */ 82 if (arg1 <= 0x200) { 83 ret = mmio_read_32(MISC1_CFG_BASE + arg1); 84 } 85 break; 86 case PLAT_MTK_DFD_WRITE_MAGIC: 87 /* only allow to access DFD register base + 0x200 */ 88 if (arg1 <= 0x200) { 89 sync_writel(MISC1_CFG_BASE + arg1, arg2); 90 } 91 break; 92 default: 93 ret = MTK_SIP_E_INVALID_PARAM; 94 break; 95 } 96 97 return ret; 98 } 99