1*27132f13SRex-BC Chen/* 2*27132f13SRex-BC Chen * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3*27132f13SRex-BC Chen * 4*27132f13SRex-BC Chen * SPDX-License-Identifier: BSD-3-Clause 5*27132f13SRex-BC Chen */ 6*27132f13SRex-BC Chen 7*27132f13SRex-BC Chen#include <arch.h> 8*27132f13SRex-BC Chen#include <asm_macros.S> 9*27132f13SRex-BC Chen#include <platform_def.h> 10*27132f13SRex-BC Chen 11*27132f13SRex-BC Chen .globl plat_is_my_cpu_primary 12*27132f13SRex-BC Chen .globl plat_my_core_pos 13*27132f13SRex-BC Chen .globl plat_mediatek_calc_core_pos 14*27132f13SRex-BC Chen 15*27132f13SRex-BC Chenfunc plat_is_my_cpu_primary 16*27132f13SRex-BC Chen mrs x0, mpidr_el1 17*27132f13SRex-BC Chen and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 18*27132f13SRex-BC Chen cmp x0, #PLAT_PRIMARY_CPU 19*27132f13SRex-BC Chen cset x0, eq 20*27132f13SRex-BC Chen ret 21*27132f13SRex-BC Chenendfunc plat_is_my_cpu_primary 22*27132f13SRex-BC Chen 23*27132f13SRex-BC Chen /* ----------------------------------------------------- 24*27132f13SRex-BC Chen * unsigned int plat_my_core_pos(void) 25*27132f13SRex-BC Chen * This function uses the plat_mediatek_calc_core_pos() 26*27132f13SRex-BC Chen * definition to get the index of the calling CPU. 27*27132f13SRex-BC Chen * ----------------------------------------------------- 28*27132f13SRex-BC Chen */ 29*27132f13SRex-BC Chenfunc plat_my_core_pos 30*27132f13SRex-BC Chen mrs x0, mpidr_el1 31*27132f13SRex-BC Chen b plat_mediatek_calc_core_pos 32*27132f13SRex-BC Chenendfunc plat_my_core_pos 33*27132f13SRex-BC Chen 34*27132f13SRex-BC Chen /* ----------------------------------------------------- 35*27132f13SRex-BC Chen * unsigned int plat_mediatek_calc_core_pos(u_register_t mpidr); 36*27132f13SRex-BC Chen * 37*27132f13SRex-BC Chen * With this function: CorePos = CoreID (AFF1) 38*27132f13SRex-BC Chen * we do it with x0 = (x0 >> 8) & 0xff 39*27132f13SRex-BC Chen * ----------------------------------------------------- 40*27132f13SRex-BC Chen */ 41*27132f13SRex-BC Chenfunc plat_mediatek_calc_core_pos 42*27132f13SRex-BC Chen mov x1, #MPIDR_AFFLVL_MASK 43*27132f13SRex-BC Chen and x0, x1, x0, lsr #MPIDR_AFF1_SHIFT 44*27132f13SRex-BC Chen ret 45*27132f13SRex-BC Chenendfunc plat_mediatek_calc_core_pos 46