1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/bl_common.h> 8 #include <common/debug.h> 9 #include <drivers/arm/gicv3.h> 10 #include <bl31/interrupt_mgmt.h> 11 #include <../drivers/arm/gic/v3/gicv3_private.h> 12 #include <mt_gic_v3.h> 13 #include <mtk_plat_common.h> 14 #include "plat_private.h" 15 #include <plat/common/platform.h> 16 #include <platform_def.h> 17 #include <stdint.h> 18 #include <stdio.h> 19 20 #define NR_INT_POL_CTL 20 21 22 uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; 23 24 /* 25 * We save and restore the GICv3 context on system suspend. Allocate the 26 * data in the designated EL3 Secure carve-out memory 27 */ 28 gicv3_redist_ctx_t rdist_ctx __section("arm_el3_tzc_dram"); 29 gicv3_dist_ctx_t dist_ctx __section("arm_el3_tzc_dram"); 30 31 32 static unsigned int mt_mpidr_to_core_pos(u_register_t mpidr) 33 { 34 return plat_core_pos_by_mpidr(mpidr); 35 } 36 37 gicv3_driver_data_t mt_gicv3_data = { 38 .gicd_base = MT_GIC_BASE, 39 .gicr_base = MT_GIC_RDIST_BASE, 40 .rdistif_num = PLATFORM_CORE_COUNT, 41 .rdistif_base_addrs = rdistif_base_addrs, 42 .mpidr_to_core_pos = mt_mpidr_to_core_pos, 43 }; 44 45 void setup_int_schedule_mode(enum irq_schedule_mode mode, 46 unsigned int active_cpu) 47 { 48 assert(mode <= HW_MODE); 49 assert(active_cpu <= 0xFF); 50 51 if (mode == HW_MODE) { 52 mmio_write_32(GIC_INT_MASK, 53 (mmio_read_32(GIC_INT_MASK) & ~(GIC500_ACTIVE_SEL_MASK)) 54 | (0x1 << GIC500_ACTIVE_SEL_SHIFT)); 55 } else if (mode == SW_MODE) { 56 mmio_write_32(GIC_INT_MASK, 57 (mmio_read_32(GIC_INT_MASK) & ~(GIC500_ACTIVE_SEL_MASK))); 58 } 59 60 mmio_write_32(GIC_INT_MASK, 61 (mmio_read_32(GIC_INT_MASK) & ~(GIC500_ACTIVE_CPU_MASK)) 62 | (active_cpu << GIC500_ACTIVE_CPU_SHIFT)); 63 return; 64 } 65 66 void clear_sec_pol_ctl_en(void) 67 { 68 unsigned int i; 69 70 /* total 19 polarity ctrl registers */ 71 for (i = 0; i <= NR_INT_POL_CTL - 1; i++) { 72 mmio_write_32((SEC_POL_CTL_EN0 + (i * 4)), 0); 73 } 74 dsb(); 75 } 76 77 void mt_gic_driver_init(void) 78 { 79 gicv3_driver_init(&mt_gicv3_data); 80 } 81 82 void mt_gic_init(void) 83 { 84 gicv3_distif_init(); 85 gicv3_rdistif_init(plat_my_core_pos()); 86 gicv3_cpuif_enable(plat_my_core_pos()); 87 88 setup_int_schedule_mode(SW_MODE, 0xf); 89 clear_sec_pol_ctl_en(); 90 } 91 92 void mt_gic_set_pending(uint32_t irq) 93 { 94 gicv3_set_interrupt_pending(irq, plat_my_core_pos()); 95 } 96 97 uint32_t mt_gic_get_pending(uint32_t irq) 98 { 99 uint32_t bit = 1 << (irq % 32); 100 101 return (mmio_read_32(gicv3_driver_data->gicd_base + 102 GICD_ISPENDR + irq / 32 * 4) & bit) ? 1 : 0; 103 } 104 105 void mt_gic_cpuif_enable(void) 106 { 107 gicv3_cpuif_enable(plat_my_core_pos()); 108 } 109 110 void mt_gic_cpuif_disable(void) 111 { 112 gicv3_cpuif_disable(plat_my_core_pos()); 113 } 114 115 void mt_gic_pcpu_init(void) 116 { 117 gicv3_rdistif_init(plat_my_core_pos()); 118 } 119 120 void mt_gic_irq_save(void) 121 { 122 gicv3_rdistif_save(plat_my_core_pos(), &rdist_ctx); 123 gicv3_distif_save(&dist_ctx); 124 } 125 126 void mt_gic_irq_restore(void) 127 { 128 gicv3_distif_init_restore(&dist_ctx); 129 gicv3_rdistif_init_restore(plat_my_core_pos(), &rdist_ctx); 130 } 131 132 void mt_gic_sync_dcm_enable(void) 133 { 134 unsigned int val = mmio_read_32(GIC_SYNC_DCM); 135 136 val &= ~GIC_SYNC_DCM_MASK; 137 mmio_write_32(GIC_SYNC_DCM, val | GIC_SYNC_DCM_ON); 138 } 139 140 void mt_gic_sync_dcm_disable(void) 141 { 142 unsigned int val = mmio_read_32(GIC_SYNC_DCM); 143 144 val &= ~GIC_SYNC_DCM_MASK; 145 mmio_write_32(GIC_SYNC_DCM, val | GIC_SYNC_DCM_OFF); 146 } 147