1 /* 2 * Copyright (c) 2019, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/bl_common.h> 9 #include <common/debug.h> 10 #include <drivers/arm/gicv3.h> 11 #include <bl31/interrupt_mgmt.h> 12 #include <mt_gic_v3.h> 13 #include <mtk_plat_common.h> 14 #include "plat_private.h" 15 #include <plat/common/platform.h> 16 #include <platform_def.h> 17 #include <stdint.h> 18 #include <stdio.h> 19 20 #define NR_INT_POL_CTL 20 21 22 uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; 23 24 /* we save and restore the GICv3 context on system suspend */ 25 gicv3_redist_ctx_t rdist_ctx; 26 gicv3_dist_ctx_t dist_ctx; 27 28 static unsigned int mt_mpidr_to_core_pos(u_register_t mpidr) 29 { 30 return plat_core_pos_by_mpidr(mpidr); 31 } 32 33 gicv3_driver_data_t mt_gicv3_data = { 34 .gicd_base = MT_GIC_BASE, 35 .gicr_base = MT_GIC_RDIST_BASE, 36 .rdistif_num = PLATFORM_CORE_COUNT, 37 .rdistif_base_addrs = rdistif_base_addrs, 38 .mpidr_to_core_pos = mt_mpidr_to_core_pos, 39 }; 40 41 void clear_sec_pol_ctl_en(void) 42 { 43 unsigned int i; 44 45 /* total 19 polarity ctrl registers */ 46 for (i = 0; i <= NR_INT_POL_CTL - 1; i++) { 47 mmio_write_32((SEC_POL_CTL_EN0 + (i * 4)), 0); 48 } 49 dsb(); 50 } 51 52 void mt_gic_driver_init(void) 53 { 54 gicv3_driver_init(&mt_gicv3_data); 55 } 56 57 void mt_gic_init(void) 58 { 59 gicv3_distif_init(); 60 gicv3_rdistif_init(plat_my_core_pos()); 61 gicv3_cpuif_enable(plat_my_core_pos()); 62 63 clear_sec_pol_ctl_en(); 64 } 65 66 void mt_gic_set_pending(uint32_t irq) 67 { 68 gicv3_set_interrupt_pending(irq, plat_my_core_pos()); 69 } 70 71 void mt_gic_cpuif_enable(void) 72 { 73 gicv3_cpuif_enable(plat_my_core_pos()); 74 } 75 76 void mt_gic_cpuif_disable(void) 77 { 78 gicv3_cpuif_disable(plat_my_core_pos()); 79 } 80 81 void mt_gic_pcpu_init(void) 82 { 83 gicv3_rdistif_init(plat_my_core_pos()); 84 } 85 86 void mt_gic_irq_save(void) 87 { 88 gicv3_rdistif_save(plat_my_core_pos(), &rdist_ctx); 89 gicv3_distif_save(&dist_ctx); 90 } 91 92 void mt_gic_irq_restore(void) 93 { 94 gicv3_distif_init_restore(&dist_ctx); 95 gicv3_rdistif_init_restore(plat_my_core_pos(), &rdist_ctx); 96 } 97 98 void mt_gic_sync_dcm_enable(void) 99 { 100 unsigned int val = mmio_read_32(GIC_SYNC_DCM); 101 102 val &= ~GIC_SYNC_DCM_MASK; 103 mmio_write_32(GIC_SYNC_DCM, val | GIC_SYNC_DCM_ON); 104 } 105 106 void mt_gic_sync_dcm_disable(void) 107 { 108 unsigned int val = mmio_read_32(GIC_SYNC_DCM); 109 110 val &= ~GIC_SYNC_DCM_MASK; 111 mmio_write_32(GIC_SYNC_DCM, val | GIC_SYNC_DCM_OFF); 112 } 113