xref: /rk3399_ARM-atf/plat/mediatek/mt8183/plat_debug.c (revision 3fa9dec43dbf1d8862d2e6c16dfac5fe6d8d317c)
1*3fa9dec4Skenny liang /*
2*3fa9dec4Skenny liang  * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3*3fa9dec4Skenny liang  *
4*3fa9dec4Skenny liang  * SPDX-License-Identifier: BSD-3-Clause
5*3fa9dec4Skenny liang  */
6*3fa9dec4Skenny liang 
7*3fa9dec4Skenny liang #include <arch_helpers.h>
8*3fa9dec4Skenny liang #include <common/debug.h>
9*3fa9dec4Skenny liang #include <lib/mmio.h>
10*3fa9dec4Skenny liang #include <plat_debug.h>
11*3fa9dec4Skenny liang #include <platform_def.h>
12*3fa9dec4Skenny liang 
13*3fa9dec4Skenny liang void circular_buffer_setup(void)
14*3fa9dec4Skenny liang {
15*3fa9dec4Skenny liang 	/* Clear DBG_CONTROL.lastpc_disable to enable circular buffer */
16*3fa9dec4Skenny liang 	sync_writel(CA15M_DBG_CONTROL,
17*3fa9dec4Skenny liang 		    mmio_read_32(CA15M_DBG_CONTROL) & ~(BIT_CA15M_LASTPC_DIS));
18*3fa9dec4Skenny liang }
19*3fa9dec4Skenny liang 
20*3fa9dec4Skenny liang void circular_buffer_unlock(void)
21*3fa9dec4Skenny liang {
22*3fa9dec4Skenny liang 	unsigned int i;
23*3fa9dec4Skenny liang 
24*3fa9dec4Skenny liang 	/* Disable big vproc external off (set CPU_EXT_BUCK_ISO to 0x0) */
25*3fa9dec4Skenny liang 	sync_writel(VPROC_EXT_CTL, mmio_read_32(VPROC_EXT_CTL) & ~(0x1 << 1));
26*3fa9dec4Skenny liang 
27*3fa9dec4Skenny liang 	/* Release vproc apb mask (set 0x0C53_2008[1] to 0x0) */
28*3fa9dec4Skenny liang 	sync_writel(CA15M_PWR_RST_CTL, mmio_read_32(CA15M_PWR_RST_CTL) & ~(0x1 << 1));
29*3fa9dec4Skenny liang 
30*3fa9dec4Skenny liang 	for (i = 1; i <= 4; ++i)
31*3fa9dec4Skenny liang 		sync_writel(MP1_CPUTOP_PWR_CON + i * 4,
32*3fa9dec4Skenny liang 			    (mmio_read_32(MP1_CPUTOP_PWR_CON + i * 4) & ~(0x4))|(0x4));
33*3fa9dec4Skenny liang 
34*3fa9dec4Skenny liang 	/* Set DFD.en */
35*3fa9dec4Skenny liang 	sync_writel(DFD_INTERNAL_CTL, 0x1);
36*3fa9dec4Skenny liang }
37*3fa9dec4Skenny liang 
38*3fa9dec4Skenny liang void circular_buffer_lock(void)
39*3fa9dec4Skenny liang {
40*3fa9dec4Skenny liang 	/* Clear DFD.en */
41*3fa9dec4Skenny liang 	sync_writel(DFD_INTERNAL_CTL, 0x0);
42*3fa9dec4Skenny liang }
43*3fa9dec4Skenny liang 
44*3fa9dec4Skenny liang void clear_all_on_mux(void)
45*3fa9dec4Skenny liang {
46*3fa9dec4Skenny liang 	sync_writel(MCU_ALL_PWR_ON_CTRL,
47*3fa9dec4Skenny liang 		    mmio_read_32(MCU_ALL_PWR_ON_CTRL) & ~(1 << 2));
48*3fa9dec4Skenny liang 	sync_writel(MCU_ALL_PWR_ON_CTRL,
49*3fa9dec4Skenny liang 		    mmio_read_32(MCU_ALL_PWR_ON_CTRL) & ~(1 << 1));
50*3fa9dec4Skenny liang }
51*3fa9dec4Skenny liang 
52*3fa9dec4Skenny liang void l2c_parity_check_setup(void)
53*3fa9dec4Skenny liang {
54*3fa9dec4Skenny liang 	/* Enable DBG_CONTROL.l2parity_en */
55*3fa9dec4Skenny liang 	sync_writel(CA15M_DBG_CONTROL,
56*3fa9dec4Skenny liang 		    mmio_read_32(CA15M_DBG_CONTROL) | BIT_CA15M_L2PARITY_EN);
57*3fa9dec4Skenny liang }
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