xref: /rk3399_ARM-atf/plat/mediatek/mt8183/include/sspm_reg.h (revision 3ea2cc00fc0fdeef0e84a80202964609479349cd)
1*539061b8Skenny liang /*
2*539061b8Skenny liang  * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3*539061b8Skenny liang  *
4*539061b8Skenny liang  * SPDX-License-Identifier: BSD-3-Clause
5*539061b8Skenny liang  */
6*539061b8Skenny liang 
7*539061b8Skenny liang #ifndef __SSPM_REG_H__
8*539061b8Skenny liang #define __SSPM_REG_H__
9*539061b8Skenny liang 
10*539061b8Skenny liang #include "platform_def.h"
11*539061b8Skenny liang 
12*539061b8Skenny liang #define SSPM_CFGREG_RSV_RW_REG0        (SSPM_CFGREG_BASE + 0x0100)
13*539061b8Skenny liang #define SSPM_CFGREG_ACAO_INT_SET       (SSPM_CFGREG_BASE + 0x00D8)
14*539061b8Skenny liang #define SSPM_CFGREG_ACAO_INT_CLR       (SSPM_CFGREG_BASE + 0x00DC)
15*539061b8Skenny liang #define SSPM_CFGREG_ACAO_WAKEUP_EN     (SSPM_CFGREG_BASE + 0x0204)
16*539061b8Skenny liang 
17*539061b8Skenny liang #define STANDBYWFI_EN(n)               (1 << (n +  8))
18*539061b8Skenny liang #define GIC_IRQOUT_EN(n)               (1 << (n +  0))
19*539061b8Skenny liang 
20*539061b8Skenny liang #define NF_MCDI_MBOX                            19
21*539061b8Skenny liang #define MCDI_MBOX_CLUSTER_0_CAN_POWER_OFF       0
22*539061b8Skenny liang #define MCDI_MBOX_CLUSTER_1_CAN_POWER_OFF       1
23*539061b8Skenny liang #define MCDI_MBOX_BUCK_POWER_OFF_MASK           2
24*539061b8Skenny liang #define MCDI_MBOX_CLUSTER_0_ATF_ACTION_DONE     3
25*539061b8Skenny liang #define MCDI_MBOX_CLUSTER_1_ATF_ACTION_DONE     4
26*539061b8Skenny liang #define MCDI_MBOX_BOOTADDR                      5
27*539061b8Skenny liang #define MCDI_MBOX_PAUSE_ACTION                  6
28*539061b8Skenny liang #define MCDI_MBOX_AVAIL_CPU_MASK                7
29*539061b8Skenny liang #define MCDI_MBOX_CPU_CLUSTER_PWR_STAT          8
30*539061b8Skenny liang #define MCDI_MBOX_ACTION_STAT                   9
31*539061b8Skenny liang #define MCDI_MBOX_CLUSTER_0_CNT                 10
32*539061b8Skenny liang #define MCDI_MBOX_CLUSTER_1_CNT                 11
33*539061b8Skenny liang #define MCDI_MBOX_CPU_ISOLATION_MASK            12
34*539061b8Skenny liang #define MCDI_MBOX_PAUSE_ACK                     13
35*539061b8Skenny liang #define MCDI_MBOX_PENDING_ON_EVENT              14
36*539061b8Skenny liang #define MCDI_MBOX_PROF_CMD                      15
37*539061b8Skenny liang #define MCDI_MBOX_DRCC_CALI_DONE                16
38*539061b8Skenny liang #define MCDI_MBOX_HP_CMD                        17
39*539061b8Skenny liang #define MCDI_MBOX_HP_ACK                        18
40*539061b8Skenny liang 
41*539061b8Skenny liang #endif /* __SSPM_REG_H__ */
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