1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <drivers/arm/gic_common.h> 12 13 #define PLAT_PRIMARY_CPU 0x0 14 15 #define IO_PHYS 0x10000000 16 #define INFRACFG_AO_BASE (IO_PHYS + 0x1000) 17 #define PERI_BASE (IO_PHYS + 0x3000) 18 #define GPIO_BASE (IO_PHYS + 0x5000) 19 #define SPM_BASE (IO_PHYS + 0x6000) 20 #define SLEEP_REG_MD_BASE (IO_PHYS + 0xf000) 21 #define RGU_BASE (IO_PHYS + 0x7000) 22 #define I2C4_BASE_SE (IO_PHYS + 0x1008000) 23 #define I2C2_BASE_SE (IO_PHYS + 0x1009000) 24 #define PMIC_WRAP_BASE (IO_PHYS + 0xd000) 25 #define MCUCFG_BASE 0x0c530000 26 #define CFG_SF_CTRL 0x0c510014 27 #define CFG_SF_INI 0x0c510010 28 #define EMI_BASE (IO_PHYS + 0x219000) 29 #define EMI_MPU_BASE (IO_PHYS + 0x226000) 30 #define TRNG_base (IO_PHYS + 0x20f000) 31 #define MT_GIC_BASE 0x0c000000 32 #define PLAT_MT_CCI_BASE 0x0c500000 33 #define CCI_SIZE 0x00010000 34 #define EINT_BASE 0x1000b000 35 #define DVFSRC_BASE (IO_PHYS + 0x12000) 36 37 #define SSPM_CFGREG_BASE (IO_PHYS + 0x440000) 38 #define SSPM_MBOX_3_BASE (IO_PHYS + 0x480000) 39 40 #define INFRACFG_AO_BASE (IO_PHYS + 0x1000) 41 42 #define APMIXEDSYS (IO_PHYS + 0xC000) 43 #define ARMPLL_LL_CON0 (APMIXEDSYS + 0x200) 44 #define ARMPLL_L_CON0 (APMIXEDSYS + 0x210) 45 #define ARMPLL_L_PWR_CON0 (APMIXEDSYS + 0x21c) 46 #define MAINPLL_CON0 (APMIXEDSYS + 0x220) 47 #define CCIPLL_CON0 (APMIXEDSYS + 0x290) 48 49 #define TOP_CKMUXSEL (INFRACFG_AO_BASE + 0x0) 50 51 #define armpll_mux1_sel_big_mask (0xf << 4) 52 #define armpll_mux1_sel_big_ARMSPLL (0x1 << 4) 53 #define armpll_mux1_sel_sml_mask (0xf << 8) 54 #define armpll_mux1_sel_sml_ARMSPLL (0x1 << 8) 55 56 57 /* Aggregate of all devices in the first GB */ 58 #define MTK_DEV_RNG0_BASE IO_PHYS 59 #define MTK_DEV_RNG0_SIZE 0x490000 60 #define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000) 61 #define MTK_DEV_RNG1_SIZE 0x4000000 62 #define MTK_DEV_RNG2_BASE 0x0c000000 63 #define MTK_DEV_RNG2_SIZE 0x600000 64 #define MT_MCUSYS_SIZE 0x90000 65 #define RAM_CONSOLE_BASE 0x11d000 66 #define RAM_CONSOLE_SIZE 0x1000 67 68 /******************************************************************************* 69 * MSDC 70 ******************************************************************************/ 71 #define MSDC0_BASE (IO_PHYS + 0x01230000) 72 73 /******************************************************************************* 74 * MCUSYS related constants 75 ******************************************************************************/ 76 #define MT_L2_WRITE_ACCESS_RATE (MCUCFG_BASE + 0x604) 77 #define MP0_CA7L_CACHE_CONFIG (MCUCFG_BASE + 0x7f0) 78 #define MP1_CA7L_CACHE_CONFIG (MCUCFG_BASE + 0x7f4) 79 #define EMI_WFIFO (MCUCFG_BASE + 0x0b5c) 80 81 /******************************************************************************* 82 * GIC related constants 83 ******************************************************************************/ 84 #define MT_POLARITY_LOW 0 85 #define MT_POLARITY_HIGH 1 86 #define MT_EDGE_SENSITIVE 1 87 #define MT_LEVEL_SENSITIVE 0 88 89 /******************************************************************************* 90 * UART related constants 91 ******************************************************************************/ 92 #define UART0_BASE (IO_PHYS + 0x01002000) 93 #define UART1_BASE (IO_PHYS + 0x01003000) 94 95 #define UART_BAUDRATE 115200 96 #define UART_CLOCK 26000000 97 98 /******************************************************************************* 99 * System counter frequency related constants 100 ******************************************************************************/ 101 #define SYS_COUNTER_FREQ_IN_TICKS 13000000 102 #define SYS_COUNTER_FREQ_IN_MHZ 13 103 104 /******************************************************************************* 105 * GIC-400 & interrupt handling related constants 106 ******************************************************************************/ 107 108 /* Base MTK_platform compatible GIC memory map */ 109 #define BASE_GICD_BASE MT_GIC_BASE 110 #define BASE_GICC_BASE (MT_GIC_BASE + 0x400000) 111 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x100000) 112 #define BASE_GICR_BASE (MT_GIC_BASE + 0x100000) 113 #define BASE_GICH_BASE (MT_GIC_BASE + 0x4000) 114 #define BASE_GICV_BASE (MT_GIC_BASE + 0x6000) 115 #define INT_POL_CTL0 (MCUCFG_BASE + 0xa80) 116 #define SEC_POL_CTL_EN0 (MCUCFG_BASE + 0xa00) 117 #define GIC_SYNC_DCM (MCUCFG_BASE + 0x758) 118 #define GIC_SYNC_DCM_MASK 0x3 119 #define GIC_SYNC_DCM_ON 0x3 120 #define GIC_SYNC_DCM_OFF 0x0 121 #define GIC_PRIVATE_SIGNALS 32 122 123 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 124 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 125 126 #define PLAT_ARM_G1S_IRQ_PROPS(grp) ( \ 127 INTR_PROP_DESC(MT_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 128 GIC_INTR_CFG_EDGE), \ 129 INTR_PROP_DESC(MT_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 130 GIC_INTR_CFG_EDGE), \ 131 INTR_PROP_DESC(MT_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 132 GIC_INTR_CFG_EDGE), \ 133 INTR_PROP_DESC(MT_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 134 GIC_INTR_CFG_EDGE), \ 135 INTR_PROP_DESC(MT_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 136 GIC_INTR_CFG_EDGE), \ 137 INTR_PROP_DESC(MT_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 138 GIC_INTR_CFG_EDGE), \ 139 INTR_PROP_DESC(MT_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 140 GIC_INTR_CFG_EDGE), \ 141 INTR_PROP_DESC(MT_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 142 GIC_INTR_CFG_EDGE)) \ 143 144 #define PLAT_ARM_G0_IRQ_PROPS(grp) 145 146 /******************************************************************************* 147 * CCI-400 related constants 148 ******************************************************************************/ 149 #define PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX 4 150 #define PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 3 151 152 /******************************************************************************* 153 * WDT Registers 154 ******************************************************************************/ 155 #define MTK_WDT_BASE (IO_PHYS + 0x00007000) 156 #define MTK_WDT_SIZE 0x1000 157 #define MTK_WDT_MODE (MTK_WDT_BASE + 0x0000) 158 #define MTK_WDT_LENGTH (MTK_WDT_BASE + 0x0004) 159 #define MTK_WDT_RESTART (MTK_WDT_BASE + 0x0008) 160 #define MTK_WDT_STATUS (MTK_WDT_BASE + 0x000C) 161 #define MTK_WDT_INTERVAL (MTK_WDT_BASE + 0x0010) 162 #define MTK_WDT_SWRST (MTK_WDT_BASE + 0x0014) 163 #define MTK_WDT_SWSYSRST (MTK_WDT_BASE + 0x0018) 164 #define MTK_WDT_NONRST_REG (MTK_WDT_BASE + 0x0020) 165 #define MTK_WDT_NONRST_REG2 (MTK_WDT_BASE + 0x0024) 166 #define MTK_WDT_REQ_MODE (MTK_WDT_BASE + 0x0030) 167 #define MTK_WDT_REQ_IRQ_EN (MTK_WDT_BASE + 0x0034) 168 #define MTK_WDT_EXT_REQ_CON (MTK_WDT_BASE + 0x0038) 169 #define MTK_WDT_DEBUG_CTL (MTK_WDT_BASE + 0x0040) 170 #define MTK_WDT_LATCH_CTL (MTK_WDT_BASE + 0x0044) 171 #define MTK_WDT_DEBUG_CTL2 (MTK_WDT_BASE + 0x00A0) 172 #define MTK_WDT_COUNTER (MTK_WDT_BASE + 0x0514) 173 174 /* WDT_STATUS */ 175 #define MTK_WDT_STATUS_SPM_THERMAL_RST (1 << 0) 176 #define MTK_WDT_STATUS_SPM_RST (1 << 1) 177 #define MTK_WDT_STATUS_EINT_RST (1 << 2) 178 #define MTK_WDT_STATUS_SYSRST_RST (1 << 3) /* from PMIC */ 179 #define MTK_WDT_STATUS_DVFSP_RST (1 << 4) 180 #define MTK_WDT_STATUS_PMCU_RST (1 << 16) 181 #define MTK_WDT_STATUS_MDDBG_RST (1 << 17) 182 #define MTK_WDT_STATUS_THERMAL_DIRECT_RST (1 << 18) 183 #define MTK_WDT_STATUS_DEBUG_RST (1 << 19) 184 #define MTK_WDT_STATUS_SECURITY_RST (1 << 28) 185 #define MTK_WDT_STATUS_IRQ_ASSERT (1 << 29) 186 #define MTK_WDT_STATUS_SW_WDT_RST (1 << 30) 187 #define MTK_WDT_STATUS_HW_WDT_RST (1U << 31) 188 189 /* RGU other related */ 190 #define MTK_WDT_MODE_DUAL_MODE 0x0040 191 #define MTK_WDT_MODE_IRQ 0x0008 192 #define MTK_WDT_MODE_KEY 0x22000000 193 #define MTK_WDT_MODE_EXTEN 0x0004 194 #define MTK_WDT_SWRST_KEY 0x1209 195 #define MTK_WDT_RESTART_KEY 0x1971 196 197 /******************************************************************************* 198 * TRNG Registers 199 ******************************************************************************/ 200 #define TRNG_BASE_ADDR TRNG_base 201 #define TRNG_BASE_SIZE 0x1000 202 #define TRNG_CTRL (TRNG_base + 0x0000) 203 #define TRNG_TIME (TRNG_base + 0x0004) 204 #define TRNG_DATA (TRNG_base + 0x0008) 205 #define TRNG_PDN_base 0x10001000 206 #define TRNG_PDN_BASE_ADDR TRNG_PDN_BASE_ADDR 207 #define TRNG_PDN_BASE_SIZE 0x1000 208 #define TRNG_PDN_SET (TRNG_PDN_base + 0x0088) 209 #define TRNG_PDN_CLR (TRNG_PDN_base + 0x008c) 210 #define TRNG_PDN_STATUS (TRNG_PDN_base + 0x0094) 211 #define TRNG_CTRL_RDY 0x80000000 212 #define TRNG_CTRL_START 0x00000001 213 #define TRNG_PDN_VALUE 0x200 214 215 /* FIQ platform related define */ 216 #define MT_IRQ_SEC_SGI_0 8 217 #define MT_IRQ_SEC_SGI_1 9 218 #define MT_IRQ_SEC_SGI_2 10 219 #define MT_IRQ_SEC_SGI_3 11 220 #define MT_IRQ_SEC_SGI_4 12 221 #define MT_IRQ_SEC_SGI_5 13 222 #define MT_IRQ_SEC_SGI_6 14 223 #define MT_IRQ_SEC_SGI_7 15 224 225 #define FIQ_SMP_CALL_SGI 13 226 #define WDT_IRQ_BIT_ID 174 227 #define ATF_LOG_IRQ_ID 277 228 229 #define ATF_AMMS_IRQ_ID 338 230 #define PCCIF1_IRQ0_BIT_ID 185 231 #define PCCIF1_IRQ1_BIT_ID 186 232 233 #define DEBUG_XLAT_TABLE 0 234 235 /******************************************************************************* 236 * Platform binary types for linking 237 ******************************************************************************/ 238 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 239 #define PLATFORM_LINKER_ARCH aarch64 240 241 /******************************************************************************* 242 * Generic platform constants 243 ******************************************************************************/ 244 245 /* Size of cacheable stacks */ 246 #if DEBUG_XLAT_TABLE 247 #define PLATFORM_STACK_SIZE 0x800 248 #elif IMAGE_BL1 249 #define PLATFORM_STACK_SIZE 0x440 250 #elif IMAGE_BL2 251 #define PLATFORM_STACK_SIZE 0x400 252 #elif IMAGE_BL31 253 #define PLATFORM_STACK_SIZE 0x800 254 #elif IMAGE_BL32 255 #define PLATFORM_STACK_SIZE 0x440 256 #endif 257 258 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 259 #define PLAT_MAX_PWR_LVL U(2) 260 #define PLAT_MAX_RET_STATE U(1) 261 #define PLAT_MAX_OFF_STATE U(2) 262 263 #define PLATFORM_CACHE_LINE_SIZE 64 264 #define PLATFORM_SYSTEM_COUNT 1 265 #define PLATFORM_CLUSTER_COUNT 2 266 #define PLATFORM_CLUSTER0_CORE_COUNT 4 267 #define PLATFORM_CLUSTER1_CORE_COUNT 4 268 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 269 PLATFORM_CLUSTER0_CORE_COUNT) 270 #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 271 #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 272 PLATFORM_CLUSTER_COUNT + \ 273 PLATFORM_CORE_COUNT) 274 275 /******************************************************************************* 276 * Platform memory map related constants 277 ******************************************************************************/ 278 279 #define TZRAM_BASE 0x54600000 280 #define TZRAM_SIZE 0x00030000 281 282 /******************************************************************************* 283 * BL31 specific defines. 284 ******************************************************************************/ 285 /* 286 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 287 * present). BL31_BASE is calculated using the current BL31 debug size plus a 288 * little space for growth. 289 */ 290 #define BL31_BASE (TZRAM_BASE + 0x1000) 291 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 292 293 /******************************************************************************* 294 * Platform specific page table and MMU setup constants 295 ******************************************************************************/ 296 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 297 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 298 #define MAX_XLAT_TABLES 16 299 #define MAX_MMAP_REGIONS 16 300 301 /******************************************************************************* 302 * Declarations and constants to access the mailboxes safely. Each mailbox is 303 * aligned on the biggest cache line size in the platform. This is known only 304 * to the platform as it might have a combination of integrated and external 305 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 306 * line at any cache level. They could belong to different cpus/clusters & 307 * get written while being protected by different locks causing corruption of 308 * a valid mailbox address. 309 ******************************************************************************/ 310 #define CACHE_WRITEBACK_SHIFT 6 311 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 312 #endif /* PLATFORM_DEF_H */ 313