1*7352f329Skenny liang /* 2*7352f329Skenny liang * Copyright (c) 2019, MediaTek Inc. All rights reserved. 3*7352f329Skenny liang * 4*7352f329Skenny liang * SPDX-License-Identifier: BSD-3-Clause 5*7352f329Skenny liang */ 6*7352f329Skenny liang 7*7352f329Skenny liang #ifndef PLAT_DCM_H 8*7352f329Skenny liang #define PLAT_DCM_H 9*7352f329Skenny liang 10*7352f329Skenny liang #define MP2_SYNC_DCM (MCUCFG_BASE + 0x2274) 11*7352f329Skenny liang #define MP2_SYNC_DCM_MASK (0x1 << 0) 12*7352f329Skenny liang #define MP2_SYNC_DCM_ON (0x1 << 0) 13*7352f329Skenny liang #define MP2_SYNC_DCM_OFF (0x0 << 0) 14*7352f329Skenny liang 15*7352f329Skenny liang extern uint64_t plat_dcm_mcsi_a_addr; 16*7352f329Skenny liang extern uint32_t plat_dcm_mcsi_a_val; 17*7352f329Skenny liang extern int plat_dcm_initiated; 18*7352f329Skenny liang 19*7352f329Skenny liang extern void plat_dcm_mcsi_a_backup(void); 20*7352f329Skenny liang extern void plat_dcm_mcsi_a_restore(void); 21*7352f329Skenny liang extern void plat_dcm_rgu_enable(void); 22*7352f329Skenny liang extern void plat_dcm_restore_cluster_on(unsigned long mpidr); 23*7352f329Skenny liang extern void plat_dcm_msg_handler(uint64_t x1); 24*7352f329Skenny liang extern unsigned long plat_dcm_get_enabled_cnt(uint64_t type); 25*7352f329Skenny liang extern void plat_dcm_init(void); 26*7352f329Skenny liang 27*7352f329Skenny liang #define ALL_DCM_TYPE (ARMCORE_DCM_TYPE | MCUSYS_DCM_TYPE \ 28*7352f329Skenny liang | STALL_DCM_TYPE | BIG_CORE_DCM_TYPE \ 29*7352f329Skenny liang | GIC_SYNC_DCM_TYPE | RGU_DCM_TYPE \ 30*7352f329Skenny liang | INFRA_DCM_TYPE \ 31*7352f329Skenny liang | DDRPHY_DCM_TYPE | EMI_DCM_TYPE | DRAMC_DCM_TYPE \ 32*7352f329Skenny liang | MCSI_DCM_TYPE) 33*7352f329Skenny liang 34*7352f329Skenny liang enum { 35*7352f329Skenny liang ARMCORE_DCM_TYPE = (1U << 0), 36*7352f329Skenny liang MCUSYS_DCM_TYPE = (1U << 1), 37*7352f329Skenny liang INFRA_DCM_TYPE = (1U << 2), 38*7352f329Skenny liang PERI_DCM_TYPE = (1U << 3), 39*7352f329Skenny liang EMI_DCM_TYPE = (1U << 4), 40*7352f329Skenny liang DRAMC_DCM_TYPE = (1U << 5), 41*7352f329Skenny liang DDRPHY_DCM_TYPE = (1U << 6), 42*7352f329Skenny liang STALL_DCM_TYPE = (1U << 7), 43*7352f329Skenny liang BIG_CORE_DCM_TYPE = (1U << 8), 44*7352f329Skenny liang GIC_SYNC_DCM_TYPE = (1U << 9), 45*7352f329Skenny liang LAST_CORE_DCM_TYPE = (1U << 10), 46*7352f329Skenny liang RGU_DCM_TYPE = (1U << 11), 47*7352f329Skenny liang TOPCKG_DCM_TYPE = (1U << 12), 48*7352f329Skenny liang LPDMA_DCM_TYPE = (1U << 13), 49*7352f329Skenny liang MCSI_DCM_TYPE = (1U << 14), 50*7352f329Skenny liang NR_DCM_TYPE = 15, 51*7352f329Skenny liang }; 52*7352f329Skenny liang 53*7352f329Skenny liang #endif /* PLAT_DCM_H */