1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT_GIC_V3_H 8 #define MT_GIC_V3_H 9 10 #include <lib/mmio.h> 11 12 enum irq_schedule_mode { 13 SW_MODE, 14 HW_MODE 15 }; 16 17 #define GIC_INT_MASK (MCUCFG_BASE + 0x5e8) 18 #define GIC500_ACTIVE_SEL_SHIFT 3 19 #define GIC500_ACTIVE_SEL_MASK (0x7 << GIC500_ACTIVE_SEL_SHIFT) 20 #define GIC500_ACTIVE_CPU_SHIFT 16 21 #define GIC500_ACTIVE_CPU_MASK (0xff << GIC500_ACTIVE_CPU_SHIFT) 22 23 void mt_gic_driver_init(void); 24 void mt_gic_init(void); 25 void mt_gic_set_pending(uint32_t irq); 26 uint32_t mt_gic_get_pending(uint32_t irq); 27 void mt_gic_cpuif_enable(void); 28 void mt_gic_cpuif_disable(void); 29 void mt_gic_pcpu_init(void); 30 void mt_gic_irq_save(void); 31 void mt_gic_irq_restore(void); 32 void mt_gic_sync_dcm_enable(void); 33 void mt_gic_sync_dcm_disable(void); 34 35 #endif /* MT_GIC_V3_H */ 36