1*28a773efSkenny liang /* 2*28a773efSkenny liang * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3*28a773efSkenny liang * 4*28a773efSkenny liang * SPDX-License-Identifier: BSD-3-Clause 5*28a773efSkenny liang */ 6*28a773efSkenny liang 7*28a773efSkenny liang #ifndef MT_GIC_V3_H 8*28a773efSkenny liang #define MT_GIC_V3_H 9*28a773efSkenny liang 10*28a773efSkenny liang #include <lib/mmio.h> 11*28a773efSkenny liang 12*28a773efSkenny liang enum irq_schedule_mode { 13*28a773efSkenny liang SW_MODE, 14*28a773efSkenny liang HW_MODE 15*28a773efSkenny liang }; 16*28a773efSkenny liang 17*28a773efSkenny liang #define GIC_INT_MASK (MCUCFG_BASE + 0x5e8) 18*28a773efSkenny liang #define GIC500_ACTIVE_SEL_SHIFT 3 19*28a773efSkenny liang #define GIC500_ACTIVE_SEL_MASK (0x7 << GIC500_ACTIVE_SEL_SHIFT) 20*28a773efSkenny liang #define GIC500_ACTIVE_CPU_SHIFT 16 21*28a773efSkenny liang #define GIC500_ACTIVE_CPU_MASK (0xff << GIC500_ACTIVE_CPU_SHIFT) 22*28a773efSkenny liang 23*28a773efSkenny liang void mt_gic_driver_init(void); 24*28a773efSkenny liang void mt_gic_init(void); 25*28a773efSkenny liang void mt_gic_set_pending(uint32_t irq); 26*28a773efSkenny liang uint32_t mt_gic_get_pending(uint32_t irq); 27*28a773efSkenny liang void mt_gic_cpuif_enable(void); 28*28a773efSkenny liang void mt_gic_cpuif_disable(void); 29*28a773efSkenny liang void mt_gic_pcpu_init(void); 30*28a773efSkenny liang void mt_gic_irq_save(void); 31*28a773efSkenny liang void mt_gic_irq_restore(void); 32*28a773efSkenny liang void mt_gic_sync_dcm_enable(void); 33*28a773efSkenny liang void mt_gic_sync_dcm_disable(void); 34*28a773efSkenny liang 35*28a773efSkenny liang #endif /* MT_GIC_V3_H */ 36