1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/debug.h> 8 #include <lib/mmio.h> 9 #include <platform_def.h> 10 #include <spm.h> 11 #include <spm_pmic_wrap.h> 12 #include <lib/libc/string.h> 13 14 #define SLEEP_REG_MD_SPM_DVFS_CMD20 (SLEEP_REG_MD_BASE + 0x010) 15 #define SLEEP_REG_MD_SPM_DVFS_CMD21 (SLEEP_REG_MD_BASE + 0x014) 16 #define SLEEP_REG_MD_SPM_DVFS_CMD22 (SLEEP_REG_MD_BASE + 0x018) 17 #define SLEEP_REG_MD_SPM_DVFS_CMD23 (SLEEP_REG_MD_BASE + 0x01C) 18 19 /* PMIC_WRAP -> PMIC MT6358 */ 20 #define VCORE_BASE_UV 50000 21 #define VOLT_TO_PMIC_VAL(volt) (((volt) - VCORE_BASE_UV + 625 - 1) / 625) 22 #define PMIC_VAL_TO_VOLT(pmic) (((pmic) * 625) + VCORE_BASE_UV) 23 24 #define DEFAULT_VOLT_VSRAM (100000) 25 #define DEFAULT_VOLT_VCORE (100000) 26 #define NR_PMIC_WRAP_CMD (NR_IDX_ALL) 27 #define MAX_RETRY_COUNT (100) 28 #define SPM_DATA_SHIFT (16) 29 30 #define BUCK_VCORE_ELR0 0x14AA 31 #define BUCK_VPROC12_CON0 0x1408 32 #define BUCK_VPROC11_CON0 0x1388 33 #define TOP_SPI_CON0 0x044C 34 #define LDO_VSRAM_PROC12_CON0 0x1B88 35 #define LDO_VSRAM_PROC11_CON0 0x1B46 36 #define BUCK_VMODEM_ELR0 0x15A6 37 38 struct pmic_wrap_cmd { 39 unsigned long cmd_addr; 40 unsigned long cmd_wdata; 41 }; 42 43 struct pmic_wrap_setting { 44 enum pmic_wrap_phase_id phase; 45 struct pmic_wrap_cmd addr[NR_PMIC_WRAP_CMD]; 46 struct { 47 struct { 48 unsigned long cmd_addr; 49 unsigned long cmd_wdata; 50 } _[NR_PMIC_WRAP_CMD]; 51 const int nr_idx; 52 } set[NR_PMIC_WRAP_PHASE]; 53 }; 54 55 static struct pmic_wrap_setting pw = { 56 .phase = NR_PMIC_WRAP_PHASE, 57 .addr = {{0, 0} }, 58 .set[PMIC_WRAP_PHASE_ALLINONE] = { 59 ._[CMD_0] = {BUCK_VCORE_ELR0, VOLT_TO_PMIC_VAL(70000),}, 60 ._[CMD_1] = {BUCK_VCORE_ELR0, VOLT_TO_PMIC_VAL(80000),}, 61 ._[CMD_2] = {BUCK_VPROC12_CON0, 0x3,}, 62 ._[CMD_3] = {BUCK_VPROC12_CON0, 0x1,}, 63 ._[CMD_4] = {BUCK_VPROC11_CON0, 0x3,}, 64 ._[CMD_5] = {BUCK_VPROC11_CON0, 0x1,}, 65 ._[CMD_6] = {TOP_SPI_CON0, 0x1,}, 66 ._[CMD_7] = {TOP_SPI_CON0, 0x0,}, 67 ._[CMD_8] = {BUCK_VPROC12_CON0, 0x0,}, 68 ._[CMD_9] = {BUCK_VPROC12_CON0, 0x1,}, 69 ._[CMD_10] = {BUCK_VPROC11_CON0, 0x0,}, 70 ._[CMD_11] = {BUCK_VPROC11_CON0, 0x1,}, 71 ._[CMD_12] = {LDO_VSRAM_PROC12_CON0, 0x0,}, 72 ._[CMD_13] = {LDO_VSRAM_PROC12_CON0, 0x1,}, 73 ._[CMD_14] = {LDO_VSRAM_PROC11_CON0, 0x0,}, 74 ._[CMD_15] = {LDO_VSRAM_PROC11_CON0, 0x1,}, 75 ._[CMD_20] = {BUCK_VMODEM_ELR0, VOLT_TO_PMIC_VAL(55000),}, 76 ._[CMD_21] = {BUCK_VCORE_ELR0, VOLT_TO_PMIC_VAL(60000),}, 77 ._[CMD_22] = {LDO_VSRAM_PROC11_CON0, 0x3,}, 78 ._[CMD_23] = {LDO_VSRAM_PROC11_CON0, 0x1,}, 79 .nr_idx = NR_IDX_ALL 80 } 81 }; 82 83 void _mt_spm_pmic_table_init(void) 84 { 85 struct pmic_wrap_cmd pwrap_cmd_default[NR_PMIC_WRAP_CMD] = { 86 {(uint32_t)SPM_DVFS_CMD0, (uint32_t)SPM_DVFS_CMD0,}, 87 {(uint32_t)SPM_DVFS_CMD1, (uint32_t)SPM_DVFS_CMD1,}, 88 {(uint32_t)SPM_DVFS_CMD2, (uint32_t)SPM_DVFS_CMD2,}, 89 {(uint32_t)SPM_DVFS_CMD3, (uint32_t)SPM_DVFS_CMD3,}, 90 {(uint32_t)SPM_DVFS_CMD4, (uint32_t)SPM_DVFS_CMD4,}, 91 {(uint32_t)SPM_DVFS_CMD5, (uint32_t)SPM_DVFS_CMD5,}, 92 {(uint32_t)SPM_DVFS_CMD6, (uint32_t)SPM_DVFS_CMD6,}, 93 {(uint32_t)SPM_DVFS_CMD7, (uint32_t)SPM_DVFS_CMD7,}, 94 {(uint32_t)SPM_DVFS_CMD8, (uint32_t)SPM_DVFS_CMD8,}, 95 {(uint32_t)SPM_DVFS_CMD9, (uint32_t)SPM_DVFS_CMD9,}, 96 {(uint32_t)SPM_DVFS_CMD10, (uint32_t)SPM_DVFS_CMD10,}, 97 {(uint32_t)SPM_DVFS_CMD11, (uint32_t)SPM_DVFS_CMD11,}, 98 {(uint32_t)SPM_DVFS_CMD12, (uint32_t)SPM_DVFS_CMD12,}, 99 {(uint32_t)SPM_DVFS_CMD13, (uint32_t)SPM_DVFS_CMD13,}, 100 {(uint32_t)SPM_DVFS_CMD14, (uint32_t)SPM_DVFS_CMD14,}, 101 {(uint32_t)SPM_DVFS_CMD15, (uint32_t)SPM_DVFS_CMD15,}, 102 {(uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD20, 103 (uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD20,}, 104 {(uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD21, 105 (uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD21,}, 106 {(uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD22, 107 (uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD22,}, 108 {(uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD23, 109 (uint32_t)SLEEP_REG_MD_SPM_DVFS_CMD23,} 110 }; 111 112 memcpy(pw.addr, pwrap_cmd_default, sizeof(pwrap_cmd_default)); 113 } 114 115 void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase) 116 { 117 uint32_t idx, addr, data; 118 119 if (phase >= NR_PMIC_WRAP_PHASE) 120 return; 121 122 if (pw.phase == phase) 123 return; 124 125 if (pw.addr[0].cmd_addr == 0) 126 _mt_spm_pmic_table_init(); 127 128 pw.phase = phase; 129 130 mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | 131 BCLK_CG_EN_LSB | MD_BCLK_CG_EN_LSB); 132 for (idx = 0; idx < pw.set[phase].nr_idx; idx++) { 133 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; 134 data = pw.set[phase]._[idx].cmd_wdata; 135 mmio_write_32(pw.addr[idx].cmd_addr, addr | data); 136 } 137 } 138 139 void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx, 140 uint32_t cmd_wdata) 141 { 142 uint32_t addr; 143 144 if (phase >= NR_PMIC_WRAP_PHASE) 145 return; 146 147 if (idx >= pw.set[phase].nr_idx) 148 return; 149 150 pw.set[phase]._[idx].cmd_wdata = cmd_wdata; 151 152 mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | 153 BCLK_CG_EN_LSB | MD_BCLK_CG_EN_LSB); 154 if (pw.phase == phase) { 155 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; 156 mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata); 157 } 158 } 159 160 uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, uint32_t idx) 161 { 162 if (phase >= NR_PMIC_WRAP_PHASE) 163 return 0; 164 165 if (idx >= pw.set[phase].nr_idx) 166 return 0; 167 168 return pw.set[phase]._[idx].cmd_wdata; 169 } 170 171