1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <lib/bakery_lock.h> 7 #include <common/debug.h> 8 #include <drivers/delay_timer.h> 9 #include <lib/mmio.h> 10 #include <spm.h> 11 #include <spm_pmic_wrap.h> 12 13 DEFINE_BAKERY_LOCK(spm_lock); 14 15 /* CLK_SCP_CFG_0 */ 16 #define SPM_CK_OFF_CONTROL (0x3FF) 17 18 /* CLK_SCP_CFG_1 */ 19 #define SPM_AXI_26M_SEL (0x1) 20 21 /* AP_PLL_CON3 */ 22 #define SPM_PLL_CONTROL (0x7FAAAAF) 23 24 /* AP_PLL_CON4 */ 25 #define SPM_PLL_OUT_OFF_CONTROL (0xFA0A) 26 27 /* AP_PLL_CON6 */ 28 #define PLL_DLY (0x20000) 29 30 const char *wakeup_src_str[32] = { 31 [0] = "R12_PCM_TIMER", 32 [1] = "R12_SSPM_WDT_EVENT_B", 33 [2] = "R12_KP_IRQ_B", 34 [3] = "R12_APWDT_EVENT_B", 35 [4] = "R12_APXGPT1_EVENT_B", 36 [5] = "R12_CONN2AP_SPM_WAKEUP_B", 37 [6] = "R12_EINT_EVENT_B", 38 [7] = "R12_CONN_WDT_IRQ_B", 39 [8] = "R12_CCIF0_EVENT_B", 40 [9] = "R12_LOWBATTERY_IRQ_B", 41 [10] = "R12_SSPM_SPM_IRQ_B", 42 [11] = "R12_SCP_SPM_IRQ_B", 43 [12] = "R12_SCP_WDT_EVENT_B", 44 [13] = "R12_PCM_WDT_WAKEUP_B", 45 [14] = "R12_USB_CDSC_B ", 46 [15] = "R12_USB_POWERDWN_B", 47 [16] = "R12_SYS_TIMER_EVENT_B", 48 [17] = "R12_EINT_EVENT_SECURE_B", 49 [18] = "R12_CCIF1_EVENT_B", 50 [19] = "R12_UART0_IRQ_B", 51 [20] = "R12_AFE_IRQ_MCU_B", 52 [21] = "R12_THERM_CTRL_EVENT_B", 53 [22] = "R12_SYS_CIRQ_IRQ_B", 54 [23] = "R12_MD2AP_PEER_EVENT_B", 55 [24] = "R12_CSYSPWREQ_B", 56 [25] = "R12_MD1_WDT_B ", 57 [26] = "R12_CLDMA_EVENT_B", 58 [27] = "R12_SEJ_WDT_GPT_B", 59 [28] = "R12_ALL_SSPM_WAKEUP_B", 60 [29] = "R12_CPU_IRQ_B", 61 [30] = "R12_CPU_WFI_AND_B" 62 }; 63 64 const char *spm_get_firmware_version(void) 65 { 66 return "DYNAMIC_SPM_FW_VERSION"; 67 } 68 69 void spm_lock_init(void) 70 { 71 bakery_lock_init(&spm_lock); 72 } 73 74 void spm_lock_get(void) 75 { 76 bakery_lock_get(&spm_lock); 77 } 78 79 void spm_lock_release(void) 80 { 81 bakery_lock_release(&spm_lock); 82 } 83 84 void spm_set_bootaddr(unsigned long bootaddr) 85 { 86 /* initialize core4~7 boot entry address */ 87 mmio_write_32(SW2SPM_MAILBOX_3, bootaddr); 88 } 89 90 void spm_set_cpu_status(int cpu) 91 { 92 if (cpu >= 0 && cpu < 4) { 93 mmio_write_32(ROOT_CPUTOP_ADDR, 0x10006204); 94 mmio_write_32(ROOT_CORE_ADDR, 0x10006208 + (cpu * 0x4)); 95 } else if (cpu >= 4 && cpu < 8) { 96 mmio_write_32(ROOT_CPUTOP_ADDR, 0x10006218); 97 mmio_write_32(ROOT_CORE_ADDR, 0x1000621c + ((cpu - 4) * 0x4)); 98 } else { 99 ERROR("%s: error cpu number %d\n", __func__, cpu); 100 } 101 } 102 103 void spm_set_power_control(const struct pwr_ctrl *pwrctrl) 104 { 105 mmio_write_32(SPM_AP_STANDBY_CON, 106 ((pwrctrl->wfi_op & 0x1) << 0) | 107 ((pwrctrl->mp0_cputop_idle_mask & 0x1) << 1) | 108 ((pwrctrl->mp1_cputop_idle_mask & 0x1) << 2) | 109 ((pwrctrl->mcusys_idle_mask & 0x1) << 4) | 110 ((pwrctrl->mm_mask_b & 0x3) << 16) | 111 ((pwrctrl->md_ddr_en_0_dbc_en & 0x1) << 18) | 112 ((pwrctrl->md_ddr_en_1_dbc_en & 0x1) << 19) | 113 ((pwrctrl->md_mask_b & 0x3) << 20) | 114 ((pwrctrl->sspm_mask_b & 0x1) << 22) | 115 ((pwrctrl->scp_mask_b & 0x1) << 23) | 116 ((pwrctrl->srcclkeni_mask_b & 0x1) << 24) | 117 ((pwrctrl->md_apsrc_1_sel & 0x1) << 25) | 118 ((pwrctrl->md_apsrc_0_sel & 0x1) << 26) | 119 ((pwrctrl->conn_ddr_en_dbc_en & 0x1) << 27) | 120 ((pwrctrl->conn_mask_b & 0x1) << 28) | 121 ((pwrctrl->conn_apsrc_sel & 0x1) << 29)); 122 123 mmio_write_32(SPM_SRC_REQ, 124 ((pwrctrl->spm_apsrc_req & 0x1) << 0) | 125 ((pwrctrl->spm_f26m_req & 0x1) << 1) | 126 ((pwrctrl->spm_infra_req & 0x1) << 3) | 127 ((pwrctrl->spm_vrf18_req & 0x1) << 4) | 128 ((pwrctrl->spm_ddren_req & 0x1) << 7) | 129 ((pwrctrl->spm_rsv_src_req & 0x7) << 8) | 130 ((pwrctrl->spm_ddren_2_req & 0x1) << 11) | 131 ((pwrctrl->cpu_md_dvfs_sop_force_on & 0x1) << 16)); 132 133 mmio_write_32(SPM_SRC_MASK, 134 ((pwrctrl->csyspwreq_mask & 0x1) << 0) | 135 ((pwrctrl->ccif0_md_event_mask_b & 0x1) << 1) | 136 ((pwrctrl->ccif0_ap_event_mask_b & 0x1) << 2) | 137 ((pwrctrl->ccif1_md_event_mask_b & 0x1) << 3) | 138 ((pwrctrl->ccif1_ap_event_mask_b & 0x1) << 4) | 139 ((pwrctrl->ccif2_md_event_mask_b & 0x1) << 5) | 140 ((pwrctrl->ccif2_ap_event_mask_b & 0x1) << 6) | 141 ((pwrctrl->ccif3_md_event_mask_b & 0x1) << 7) | 142 ((pwrctrl->ccif3_ap_event_mask_b & 0x1) << 8) | 143 ((pwrctrl->md_srcclkena_0_infra_mask_b & 0x1) << 9) | 144 ((pwrctrl->md_srcclkena_1_infra_mask_b & 0x1) << 10) | 145 ((pwrctrl->conn_srcclkena_infra_mask_b & 0x1) << 11) | 146 ((pwrctrl->ufs_infra_req_mask_b & 0x1) << 12) | 147 ((pwrctrl->srcclkeni_infra_mask_b & 0x1) << 13) | 148 ((pwrctrl->md_apsrc_req_0_infra_mask_b & 0x1) << 14) | 149 ((pwrctrl->md_apsrc_req_1_infra_mask_b & 0x1) << 15) | 150 ((pwrctrl->conn_apsrcreq_infra_mask_b & 0x1) << 16) | 151 ((pwrctrl->ufs_srcclkena_mask_b & 0x1) << 17) | 152 ((pwrctrl->md_vrf18_req_0_mask_b & 0x1) << 18) | 153 ((pwrctrl->md_vrf18_req_1_mask_b & 0x1) << 19) | 154 ((pwrctrl->ufs_vrf18_req_mask_b & 0x1) << 20) | 155 ((pwrctrl->gce_vrf18_req_mask_b & 0x1) << 21) | 156 ((pwrctrl->conn_infra_req_mask_b & 0x1) << 22) | 157 ((pwrctrl->gce_apsrc_req_mask_b & 0x1) << 23) | 158 ((pwrctrl->disp0_apsrc_req_mask_b & 0x1) << 24) | 159 ((pwrctrl->disp1_apsrc_req_mask_b & 0x1) << 25) | 160 ((pwrctrl->mfg_req_mask_b & 0x1) << 26) | 161 ((pwrctrl->vdec_req_mask_b & 0x1) << 27)); 162 163 mmio_write_32(SPM_SRC2_MASK, 164 ((pwrctrl->md_ddr_en_0_mask_b & 0x1) << 0) | 165 ((pwrctrl->md_ddr_en_1_mask_b & 0x1) << 1) | 166 ((pwrctrl->conn_ddr_en_mask_b & 0x1) << 2) | 167 ((pwrctrl->ddren_sspm_apsrc_req_mask_b & 0x1) << 3) | 168 ((pwrctrl->ddren_scp_apsrc_req_mask_b & 0x1) << 4) | 169 ((pwrctrl->disp0_ddren_mask_b & 0x1) << 5) | 170 ((pwrctrl->disp1_ddren_mask_b & 0x1) << 6) | 171 ((pwrctrl->gce_ddren_mask_b & 0x1) << 7) | 172 ((pwrctrl->ddren_emi_self_refresh_ch0_mask_b & 0x1) 173 << 8) | 174 ((pwrctrl->ddren_emi_self_refresh_ch1_mask_b & 0x1) 175 << 9)); 176 177 mmio_write_32(SPM_WAKEUP_EVENT_MASK, 178 ((pwrctrl->spm_wakeup_event_mask & 0xffffffff) << 0)); 179 180 mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK, 181 ((pwrctrl->spm_wakeup_event_ext_mask & 0xffffffff) 182 << 0)); 183 184 mmio_write_32(SPM_SRC3_MASK, 185 ((pwrctrl->md_ddr_en_2_0_mask_b & 0x1) << 0) | 186 ((pwrctrl->md_ddr_en_2_1_mask_b & 0x1) << 1) | 187 ((pwrctrl->conn_ddr_en_2_mask_b & 0x1) << 2) | 188 ((pwrctrl->ddren2_sspm_apsrc_req_mask_b & 0x1) << 3) | 189 ((pwrctrl->ddren2_scp_apsrc_req_mask_b & 0x1) << 4) | 190 ((pwrctrl->disp0_ddren2_mask_b & 0x1) << 5) | 191 ((pwrctrl->disp1_ddren2_mask_b & 0x1) << 6) | 192 ((pwrctrl->gce_ddren2_mask_b & 0x1) << 7) | 193 ((pwrctrl->ddren2_emi_self_refresh_ch0_mask_b & 0x1) 194 << 8) | 195 ((pwrctrl->ddren2_emi_self_refresh_ch1_mask_b & 0x1) 196 << 9)); 197 198 mmio_write_32(MP0_CPU0_WFI_EN, 199 ((pwrctrl->mp0_cpu0_wfi_en & 0x1) << 0)); 200 mmio_write_32(MP0_CPU1_WFI_EN, 201 ((pwrctrl->mp0_cpu1_wfi_en & 0x1) << 0)); 202 mmio_write_32(MP0_CPU2_WFI_EN, 203 ((pwrctrl->mp0_cpu2_wfi_en & 0x1) << 0)); 204 mmio_write_32(MP0_CPU3_WFI_EN, 205 ((pwrctrl->mp0_cpu3_wfi_en & 0x1) << 0)); 206 207 mmio_write_32(MP1_CPU0_WFI_EN, 208 ((pwrctrl->mp1_cpu0_wfi_en & 0x1) << 0)); 209 mmio_write_32(MP1_CPU1_WFI_EN, 210 ((pwrctrl->mp1_cpu1_wfi_en & 0x1) << 0)); 211 mmio_write_32(MP1_CPU2_WFI_EN, 212 ((pwrctrl->mp1_cpu2_wfi_en & 0x1) << 0)); 213 mmio_write_32(MP1_CPU3_WFI_EN, 214 ((pwrctrl->mp1_cpu3_wfi_en & 0x1) << 0)); 215 } 216 217 void spm_disable_pcm_timer(void) 218 { 219 mmio_clrsetbits_32(PCM_CON1, PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY); 220 } 221 222 void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) 223 { 224 uint32_t val, mask, isr; 225 226 val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX; 227 mmio_write_32(PCM_TIMER_VAL, val); 228 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | PCM_TIMER_EN_LSB); 229 230 mask = pwrctrl->wake_src; 231 232 if (pwrctrl->csyspwreq_mask) 233 mask &= ~WAKE_SRC_R12_CSYSPWREQ_B; 234 235 mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask); 236 237 isr = mmio_read_32(SPM_IRQ_MASK) & SPM_TWAM_IRQ_MASK_LSB; 238 mmio_write_32(SPM_IRQ_MASK, isr | ISRM_RET_IRQ_AUX); 239 } 240 241 void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl) 242 { 243 mmio_write_32(SPM_SW_FLAG, pwrctrl->pcm_flags); 244 mmio_write_32(SPM_SW_RSV_2, pwrctrl->pcm_flags1); 245 } 246 247 void spm_set_pcm_wdt(int en) 248 { 249 if (en) { 250 mmio_clrsetbits_32(PCM_CON1, PCM_WDT_WAKE_MODE_LSB, 251 SPM_REGWR_CFG_KEY); 252 253 if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) 254 mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX); 255 mmio_write_32(PCM_WDT_VAL, 256 mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT); 257 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | PCM_WDT_EN_LSB); 258 } else { 259 mmio_clrsetbits_32(PCM_CON1, PCM_WDT_EN_LSB, 260 SPM_REGWR_CFG_KEY); 261 } 262 } 263 264 void spm_send_cpu_wakeup_event(void) 265 { 266 mmio_write_32(PCM_REG_DATA_INI, 0); 267 mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1); 268 } 269 270 void spm_get_wakeup_status(struct wake_status *wakesta) 271 { 272 wakesta->assert_pc = mmio_read_32(PCM_REG_DATA_INI); 273 wakesta->r12 = mmio_read_32(SPM_SW_RSV_0); 274 wakesta->r12_ext = mmio_read_32(PCM_REG12_EXT_DATA); 275 wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA); 276 wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA); 277 wakesta->wake_misc = mmio_read_32(SPM_BSI_D0_SR); 278 wakesta->timer_out = mmio_read_32(SPM_BSI_D1_SR); 279 wakesta->r13 = mmio_read_32(PCM_REG13_DATA); 280 wakesta->idle_sta = mmio_read_32(SUBSYS_IDLE_STA); 281 wakesta->req_sta = mmio_read_32(SRC_REQ_STA); 282 wakesta->sw_flag = mmio_read_32(SPM_SW_FLAG); 283 wakesta->sw_flag1 = mmio_read_32(SPM_SW_RSV_2); 284 wakesta->r15 = mmio_read_32(PCM_REG15_DATA); 285 wakesta->debug_flag = mmio_read_32(SPM_SW_DEBUG); 286 wakesta->debug_flag1 = mmio_read_32(WDT_LATCH_SPARE0_FIX); 287 wakesta->event_reg = mmio_read_32(SPM_BSI_D2_SR); 288 wakesta->isr = mmio_read_32(SPM_IRQ_STA); 289 } 290 291 void spm_clean_after_wakeup(void) 292 { 293 mmio_write_32(SPM_SW_RSV_0, 294 mmio_read_32(SPM_WAKEUP_STA) | 295 mmio_read_32(SPM_SW_RSV_0)); 296 mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0); 297 mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~0); 298 mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM); 299 mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM); 300 mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL); 301 } 302 303 void spm_output_wake_reason(struct wake_status *wakesta, const char *scenario) 304 { 305 uint32_t i; 306 307 if (wakesta->assert_pc != 0) { 308 INFO("%s: PCM ASSERT AT %u, ULPOSC_CON = 0x%x\n", 309 scenario, wakesta->assert_pc, mmio_read_32(ULPOSC_CON)); 310 goto spm_debug_flags; 311 } 312 313 for (i = 0; i <= 31; i++) { 314 if (wakesta->r12 & (1U << i)) { 315 INFO("%s: wake up by %s, timer_out = %u\n", 316 scenario, wakeup_src_str[i], wakesta->timer_out); 317 break; 318 } 319 } 320 321 spm_debug_flags: 322 INFO("r15 = 0x%x, r13 = 0x%x, debug_flag = 0x%x 0x%x\n", 323 wakesta->r15, wakesta->r13, wakesta->debug_flag, 324 wakesta->debug_flag1); 325 INFO("sw_flag = 0x%x 0x%x, r12 = 0x%x, r12_ext = 0x%x\n", 326 wakesta->sw_flag, wakesta->sw_flag1, wakesta->r12, 327 wakesta->r12_ext); 328 INFO("idle_sta = 0x%x, req_sta = 0x%x, event_reg = 0x%x\n", 329 wakesta->idle_sta, wakesta->req_sta, wakesta->event_reg); 330 INFO("isr = 0x%x, raw_sta = 0x%x, raw_ext_sta = 0x%x\n", 331 wakesta->isr, wakesta->raw_sta, wakesta->raw_ext_sta); 332 INFO("wake_misc = 0x%x\n", wakesta->wake_misc); 333 } 334 335 void spm_boot_init(void) 336 { 337 NOTICE("%s() start\n", __func__); 338 339 spm_lock_init(); 340 mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE); 341 342 /* switch ck_off/axi_26m control to SPM */ 343 mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_OFF_CONTROL); 344 mmio_setbits_32(CLK_SCP_CFG_1, SPM_AXI_26M_SEL); 345 346 /* switch PLL/CLKSQ control to SPM */ 347 mmio_clrbits_32(AP_PLL_CON3, SPM_PLL_CONTROL); 348 mmio_clrbits_32(AP_PLL_CON4, SPM_PLL_OUT_OFF_CONTROL); 349 mmio_clrbits_32(AP_PLL_CON6, PLL_DLY); 350 351 NOTICE("%s() end\n", __func__); 352 } 353