1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <lib/bakery_lock.h> 7 #include <common/debug.h> 8 #include <drivers/delay_timer.h> 9 #include <lib/mmio.h> 10 #include <spm.h> 11 #include <spm_pmic_wrap.h> 12 13 DEFINE_BAKERY_LOCK(spm_lock); 14 15 const char *wakeup_src_str[32] = { 16 [0] = "R12_PCM_TIMER", 17 [1] = "R12_SSPM_WDT_EVENT_B", 18 [2] = "R12_KP_IRQ_B", 19 [3] = "R12_APWDT_EVENT_B", 20 [4] = "R12_APXGPT1_EVENT_B", 21 [5] = "R12_CONN2AP_SPM_WAKEUP_B", 22 [6] = "R12_EINT_EVENT_B", 23 [7] = "R12_CONN_WDT_IRQ_B", 24 [8] = "R12_CCIF0_EVENT_B", 25 [9] = "R12_LOWBATTERY_IRQ_B", 26 [10] = "R12_SSPM_SPM_IRQ_B", 27 [11] = "R12_SCP_SPM_IRQ_B", 28 [12] = "R12_SCP_WDT_EVENT_B", 29 [13] = "R12_PCM_WDT_WAKEUP_B", 30 [14] = "R12_USB_CDSC_B ", 31 [15] = "R12_USB_POWERDWN_B", 32 [16] = "R12_SYS_TIMER_EVENT_B", 33 [17] = "R12_EINT_EVENT_SECURE_B", 34 [18] = "R12_CCIF1_EVENT_B", 35 [19] = "R12_UART0_IRQ_B", 36 [20] = "R12_AFE_IRQ_MCU_B", 37 [21] = "R12_THERM_CTRL_EVENT_B", 38 [22] = "R12_SYS_CIRQ_IRQ_B", 39 [23] = "R12_MD2AP_PEER_EVENT_B", 40 [24] = "R12_CSYSPWREQ_B", 41 [25] = "R12_MD1_WDT_B ", 42 [26] = "R12_CLDMA_EVENT_B", 43 [27] = "R12_SEJ_WDT_GPT_B", 44 [28] = "R12_ALL_SSPM_WAKEUP_B", 45 [29] = "R12_CPU_IRQ_B", 46 [30] = "R12_CPU_WFI_AND_B" 47 }; 48 49 const char *spm_get_firmware_version(void) 50 { 51 return "DYNAMIC_SPM_FW_VERSION"; 52 } 53 54 void spm_lock_init(void) 55 { 56 bakery_lock_init(&spm_lock); 57 } 58 59 void spm_lock_get(void) 60 { 61 bakery_lock_get(&spm_lock); 62 } 63 64 void spm_lock_release(void) 65 { 66 bakery_lock_release(&spm_lock); 67 } 68 69 void spm_set_bootaddr(unsigned long bootaddr) 70 { 71 /* initialize core4~7 boot entry address */ 72 mmio_write_32(SW2SPM_MAILBOX_3, bootaddr); 73 } 74 75 void spm_set_cpu_status(int cpu) 76 { 77 if (cpu >= 0 && cpu < 4) { 78 mmio_write_32(ROOT_CPUTOP_ADDR, 0x10006204); 79 mmio_write_32(ROOT_CORE_ADDR, 0x10006208 + (cpu * 0x4)); 80 } else if (cpu >= 4 && cpu < 8) { 81 mmio_write_32(ROOT_CPUTOP_ADDR, 0x10006218); 82 mmio_write_32(ROOT_CORE_ADDR, 0x1000621c + ((cpu - 4) * 0x4)); 83 } else { 84 ERROR("%s: error cpu number %d\n", __func__, cpu); 85 } 86 } 87 88 void spm_set_power_control(const struct pwr_ctrl *pwrctrl) 89 { 90 mmio_write_32(SPM_AP_STANDBY_CON, 91 ((pwrctrl->wfi_op & 0x1) << 0) | 92 ((pwrctrl->mp0_cputop_idle_mask & 0x1) << 1) | 93 ((pwrctrl->mp1_cputop_idle_mask & 0x1) << 2) | 94 ((pwrctrl->mcusys_idle_mask & 0x1) << 4) | 95 ((pwrctrl->mm_mask_b & 0x3) << 16) | 96 ((pwrctrl->md_ddr_en_0_dbc_en & 0x1) << 18) | 97 ((pwrctrl->md_ddr_en_1_dbc_en & 0x1) << 19) | 98 ((pwrctrl->md_mask_b & 0x3) << 20) | 99 ((pwrctrl->sspm_mask_b & 0x1) << 22) | 100 ((pwrctrl->scp_mask_b & 0x1) << 23) | 101 ((pwrctrl->srcclkeni_mask_b & 0x1) << 24) | 102 ((pwrctrl->md_apsrc_1_sel & 0x1) << 25) | 103 ((pwrctrl->md_apsrc_0_sel & 0x1) << 26) | 104 ((pwrctrl->conn_ddr_en_dbc_en & 0x1) << 27) | 105 ((pwrctrl->conn_mask_b & 0x1) << 28) | 106 ((pwrctrl->conn_apsrc_sel & 0x1) << 29)); 107 108 mmio_write_32(SPM_SRC_REQ, 109 ((pwrctrl->spm_apsrc_req & 0x1) << 0) | 110 ((pwrctrl->spm_f26m_req & 0x1) << 1) | 111 ((pwrctrl->spm_infra_req & 0x1) << 3) | 112 ((pwrctrl->spm_vrf18_req & 0x1) << 4) | 113 ((pwrctrl->spm_ddren_req & 0x1) << 7) | 114 ((pwrctrl->spm_rsv_src_req & 0x7) << 8) | 115 ((pwrctrl->spm_ddren_2_req & 0x1) << 11) | 116 ((pwrctrl->cpu_md_dvfs_sop_force_on & 0x1) << 16)); 117 118 mmio_write_32(SPM_SRC_MASK, 119 ((pwrctrl->csyspwreq_mask & 0x1) << 0) | 120 ((pwrctrl->ccif0_md_event_mask_b & 0x1) << 1) | 121 ((pwrctrl->ccif0_ap_event_mask_b & 0x1) << 2) | 122 ((pwrctrl->ccif1_md_event_mask_b & 0x1) << 3) | 123 ((pwrctrl->ccif1_ap_event_mask_b & 0x1) << 4) | 124 ((pwrctrl->ccif2_md_event_mask_b & 0x1) << 5) | 125 ((pwrctrl->ccif2_ap_event_mask_b & 0x1) << 6) | 126 ((pwrctrl->ccif3_md_event_mask_b & 0x1) << 7) | 127 ((pwrctrl->ccif3_ap_event_mask_b & 0x1) << 8) | 128 ((pwrctrl->md_srcclkena_0_infra_mask_b & 0x1) << 9) | 129 ((pwrctrl->md_srcclkena_1_infra_mask_b & 0x1) << 10) | 130 ((pwrctrl->conn_srcclkena_infra_mask_b & 0x1) << 11) | 131 ((pwrctrl->ufs_infra_req_mask_b & 0x1) << 12) | 132 ((pwrctrl->srcclkeni_infra_mask_b & 0x1) << 13) | 133 ((pwrctrl->md_apsrc_req_0_infra_mask_b & 0x1) << 14) | 134 ((pwrctrl->md_apsrc_req_1_infra_mask_b & 0x1) << 15) | 135 ((pwrctrl->conn_apsrcreq_infra_mask_b & 0x1) << 16) | 136 ((pwrctrl->ufs_srcclkena_mask_b & 0x1) << 17) | 137 ((pwrctrl->md_vrf18_req_0_mask_b & 0x1) << 18) | 138 ((pwrctrl->md_vrf18_req_1_mask_b & 0x1) << 19) | 139 ((pwrctrl->ufs_vrf18_req_mask_b & 0x1) << 20) | 140 ((pwrctrl->gce_vrf18_req_mask_b & 0x1) << 21) | 141 ((pwrctrl->conn_infra_req_mask_b & 0x1) << 22) | 142 ((pwrctrl->gce_apsrc_req_mask_b & 0x1) << 23) | 143 ((pwrctrl->disp0_apsrc_req_mask_b & 0x1) << 24) | 144 ((pwrctrl->disp1_apsrc_req_mask_b & 0x1) << 25) | 145 ((pwrctrl->mfg_req_mask_b & 0x1) << 26) | 146 ((pwrctrl->vdec_req_mask_b & 0x1) << 27)); 147 148 mmio_write_32(SPM_SRC2_MASK, 149 ((pwrctrl->md_ddr_en_0_mask_b & 0x1) << 0) | 150 ((pwrctrl->md_ddr_en_1_mask_b & 0x1) << 1) | 151 ((pwrctrl->conn_ddr_en_mask_b & 0x1) << 2) | 152 ((pwrctrl->ddren_sspm_apsrc_req_mask_b & 0x1) << 3) | 153 ((pwrctrl->ddren_scp_apsrc_req_mask_b & 0x1) << 4) | 154 ((pwrctrl->disp0_ddren_mask_b & 0x1) << 5) | 155 ((pwrctrl->disp1_ddren_mask_b & 0x1) << 6) | 156 ((pwrctrl->gce_ddren_mask_b & 0x1) << 7) | 157 ((pwrctrl->ddren_emi_self_refresh_ch0_mask_b & 0x1) 158 << 8) | 159 ((pwrctrl->ddren_emi_self_refresh_ch1_mask_b & 0x1) 160 << 9)); 161 162 mmio_write_32(SPM_WAKEUP_EVENT_MASK, 163 ((pwrctrl->spm_wakeup_event_mask & 0xffffffff) << 0)); 164 165 mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK, 166 ((pwrctrl->spm_wakeup_event_ext_mask & 0xffffffff) 167 << 0)); 168 169 mmio_write_32(SPM_SRC3_MASK, 170 ((pwrctrl->md_ddr_en_2_0_mask_b & 0x1) << 0) | 171 ((pwrctrl->md_ddr_en_2_1_mask_b & 0x1) << 1) | 172 ((pwrctrl->conn_ddr_en_2_mask_b & 0x1) << 2) | 173 ((pwrctrl->ddren2_sspm_apsrc_req_mask_b & 0x1) << 3) | 174 ((pwrctrl->ddren2_scp_apsrc_req_mask_b & 0x1) << 4) | 175 ((pwrctrl->disp0_ddren2_mask_b & 0x1) << 5) | 176 ((pwrctrl->disp1_ddren2_mask_b & 0x1) << 6) | 177 ((pwrctrl->gce_ddren2_mask_b & 0x1) << 7) | 178 ((pwrctrl->ddren2_emi_self_refresh_ch0_mask_b & 0x1) 179 << 8) | 180 ((pwrctrl->ddren2_emi_self_refresh_ch1_mask_b & 0x1) 181 << 9)); 182 183 mmio_write_32(MP0_CPU0_WFI_EN, 184 ((pwrctrl->mp0_cpu0_wfi_en & 0x1) << 0)); 185 mmio_write_32(MP0_CPU1_WFI_EN, 186 ((pwrctrl->mp0_cpu1_wfi_en & 0x1) << 0)); 187 mmio_write_32(MP0_CPU2_WFI_EN, 188 ((pwrctrl->mp0_cpu2_wfi_en & 0x1) << 0)); 189 mmio_write_32(MP0_CPU3_WFI_EN, 190 ((pwrctrl->mp0_cpu3_wfi_en & 0x1) << 0)); 191 192 mmio_write_32(MP1_CPU0_WFI_EN, 193 ((pwrctrl->mp1_cpu0_wfi_en & 0x1) << 0)); 194 mmio_write_32(MP1_CPU1_WFI_EN, 195 ((pwrctrl->mp1_cpu1_wfi_en & 0x1) << 0)); 196 mmio_write_32(MP1_CPU2_WFI_EN, 197 ((pwrctrl->mp1_cpu2_wfi_en & 0x1) << 0)); 198 mmio_write_32(MP1_CPU3_WFI_EN, 199 ((pwrctrl->mp1_cpu3_wfi_en & 0x1) << 0)); 200 } 201 202 void spm_disable_pcm_timer(void) 203 { 204 mmio_clrsetbits_32(PCM_CON1, PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY); 205 } 206 207 void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) 208 { 209 uint32_t val, mask, isr; 210 211 val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX; 212 mmio_write_32(PCM_TIMER_VAL, val); 213 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | PCM_TIMER_EN_LSB); 214 215 mask = pwrctrl->wake_src; 216 217 if (pwrctrl->csyspwreq_mask) 218 mask &= ~WAKE_SRC_R12_CSYSPWREQ_B; 219 220 mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask); 221 222 isr = mmio_read_32(SPM_IRQ_MASK) & SPM_TWAM_IRQ_MASK_LSB; 223 mmio_write_32(SPM_IRQ_MASK, isr | ISRM_RET_IRQ_AUX); 224 } 225 226 void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl) 227 { 228 mmio_write_32(SPM_SW_FLAG, pwrctrl->pcm_flags); 229 mmio_write_32(SPM_SW_RSV_2, pwrctrl->pcm_flags1); 230 } 231 232 void spm_set_pcm_wdt(int en) 233 { 234 if (en) { 235 mmio_clrsetbits_32(PCM_CON1, PCM_WDT_WAKE_MODE_LSB, 236 SPM_REGWR_CFG_KEY); 237 238 if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) 239 mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX); 240 mmio_write_32(PCM_WDT_VAL, 241 mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT); 242 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | PCM_WDT_EN_LSB); 243 } else { 244 mmio_clrsetbits_32(PCM_CON1, PCM_WDT_EN_LSB, 245 SPM_REGWR_CFG_KEY); 246 } 247 } 248 249 void spm_send_cpu_wakeup_event(void) 250 { 251 mmio_write_32(PCM_REG_DATA_INI, 0); 252 mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1); 253 } 254 255 void spm_get_wakeup_status(struct wake_status *wakesta) 256 { 257 wakesta->assert_pc = mmio_read_32(PCM_REG_DATA_INI); 258 wakesta->r12 = mmio_read_32(SPM_SW_RSV_0); 259 wakesta->r12_ext = mmio_read_32(PCM_REG12_EXT_DATA); 260 wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA); 261 wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA); 262 wakesta->wake_misc = mmio_read_32(SPM_BSI_D0_SR); 263 wakesta->timer_out = mmio_read_32(SPM_BSI_D1_SR); 264 wakesta->r13 = mmio_read_32(PCM_REG13_DATA); 265 wakesta->idle_sta = mmio_read_32(SUBSYS_IDLE_STA); 266 wakesta->req_sta = mmio_read_32(SRC_REQ_STA); 267 wakesta->sw_flag = mmio_read_32(SPM_SW_FLAG); 268 wakesta->sw_flag1 = mmio_read_32(SPM_SW_RSV_2); 269 wakesta->r15 = mmio_read_32(PCM_REG15_DATA); 270 wakesta->debug_flag = mmio_read_32(SPM_SW_DEBUG); 271 wakesta->debug_flag1 = mmio_read_32(WDT_LATCH_SPARE0_FIX); 272 wakesta->event_reg = mmio_read_32(SPM_BSI_D2_SR); 273 wakesta->isr = mmio_read_32(SPM_IRQ_STA); 274 } 275 276 void spm_clean_after_wakeup(void) 277 { 278 mmio_write_32(SPM_SW_RSV_0, 279 mmio_read_32(SPM_WAKEUP_STA) | 280 mmio_read_32(SPM_SW_RSV_0)); 281 mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0); 282 mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~0); 283 mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM); 284 mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM); 285 mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL); 286 } 287 288 void spm_output_wake_reason(struct wake_status *wakesta, const char *scenario) 289 { 290 uint32_t i; 291 292 if (wakesta->assert_pc != 0) { 293 INFO("%s: PCM ASSERT AT %u, ULPOSC_CON = 0x%x\n", 294 scenario, wakesta->assert_pc, mmio_read_32(ULPOSC_CON)); 295 goto spm_debug_flags; 296 } 297 298 for (i = 0; i <= 31; i++) { 299 if (wakesta->r12 & (1U << i)) { 300 INFO("%s: wake up by %s, timer_out = %u\n", 301 scenario, wakeup_src_str[i], wakesta->timer_out); 302 break; 303 } 304 } 305 306 spm_debug_flags: 307 INFO("r15 = 0x%x, r13 = 0x%x, debug_flag = 0x%x 0x%x\n", 308 wakesta->r15, wakesta->r13, wakesta->debug_flag, 309 wakesta->debug_flag1); 310 INFO("sw_flag = 0x%x 0x%x, r12 = 0x%x, r12_ext = 0x%x\n", 311 wakesta->sw_flag, wakesta->sw_flag1, wakesta->r12, 312 wakesta->r12_ext); 313 INFO("idle_sta = 0x%x, req_sta = 0x%x, event_reg = 0x%x\n", 314 wakesta->idle_sta, wakesta->req_sta, wakesta->event_reg); 315 INFO("isr = 0x%x, raw_sta = 0x%x, raw_ext_sta = 0x%x\n", 316 wakesta->isr, wakesta->raw_sta, wakesta->raw_ext_sta); 317 INFO("wake_misc = 0x%x\n", wakesta->wake_misc); 318 } 319 320 void spm_boot_init(void) 321 { 322 NOTICE("%s() start\n", __func__); 323 324 spm_lock_init(); 325 mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE); 326 327 NOTICE("%s() end\n", __func__); 328 } 329