xref: /rk3399_ARM-atf/plat/mediatek/mt8183/drivers/pmic/pmic_wrap_init.h (revision 76eac18647f3bb81e029309ea61f8c4c5336ca27)
1*e977b4dbSkenny liang /*
2*e977b4dbSkenny liang  * Copyright (c) 2019, MediaTek Inc. All rights reserved.
3*e977b4dbSkenny liang  *
4*e977b4dbSkenny liang  * SPDX-License-Identifier: BSD-3-Clause
5*e977b4dbSkenny liang  */
6*e977b4dbSkenny liang 
7*e977b4dbSkenny liang #ifndef PMIC_WRAP_INIT_H
8*e977b4dbSkenny liang #define PMIC_WRAP_INIT_H
9*e977b4dbSkenny liang 
10*e977b4dbSkenny liang #include <platform_def.h>
11*e977b4dbSkenny liang #include <stdint.h>
12*e977b4dbSkenny liang 
13*e977b4dbSkenny liang /* external API */
14*e977b4dbSkenny liang int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
15*e977b4dbSkenny liang int32_t pwrap_write(uint32_t adr, uint32_t wdata);
16*e977b4dbSkenny liang 
17*e977b4dbSkenny liang static struct mt8183_pmic_wrap_regs *const mtk_pwrap =
18*e977b4dbSkenny liang 	(void *)PMIC_WRAP_BASE;
19*e977b4dbSkenny liang 
20*e977b4dbSkenny liang /* timeout setting */
21*e977b4dbSkenny liang enum {
22*e977b4dbSkenny liang 	TIMEOUT_READ        = 255,	/* us */
23*e977b4dbSkenny liang 	TIMEOUT_WAIT_IDLE   = 255	/* us */
24*e977b4dbSkenny liang };
25*e977b4dbSkenny liang 
26*e977b4dbSkenny liang /* PMIC_WRAP registers */
27*e977b4dbSkenny liang struct mt8183_pmic_wrap_regs {
28*e977b4dbSkenny liang 	uint32_t reserved[776];
29*e977b4dbSkenny liang 	uint32_t wacs2_cmd;
30*e977b4dbSkenny liang 	uint32_t wacs2_rdata;
31*e977b4dbSkenny liang 	uint32_t wacs2_vldclr;
32*e977b4dbSkenny liang 	uint32_t reserved1[4];
33*e977b4dbSkenny liang };
34*e977b4dbSkenny liang 
35*e977b4dbSkenny liang enum {
36*e977b4dbSkenny liang 	RDATA_WACS_RDATA_SHIFT = 0,
37*e977b4dbSkenny liang 	RDATA_WACS_FSM_SHIFT = 16,
38*e977b4dbSkenny liang 	RDATA_WACS_REQ_SHIFT = 19,
39*e977b4dbSkenny liang 	RDATA_SYNC_IDLE_SHIFT,
40*e977b4dbSkenny liang 	RDATA_INIT_DONE_SHIFT,
41*e977b4dbSkenny liang 	RDATA_SYS_IDLE_SHIFT,
42*e977b4dbSkenny liang };
43*e977b4dbSkenny liang 
44*e977b4dbSkenny liang enum {
45*e977b4dbSkenny liang 	RDATA_WACS_RDATA_MASK = 0xffff,
46*e977b4dbSkenny liang 	RDATA_WACS_FSM_MASK = 0x7,
47*e977b4dbSkenny liang 	RDATA_WACS_REQ_MASK = 0x1,
48*e977b4dbSkenny liang 	RDATA_SYNC_IDLE_MASK = 0x1,
49*e977b4dbSkenny liang 	RDATA_INIT_DONE_MASK = 0x1,
50*e977b4dbSkenny liang 	RDATA_SYS_IDLE_MASK = 0x1,
51*e977b4dbSkenny liang };
52*e977b4dbSkenny liang 
53*e977b4dbSkenny liang /* WACS_FSM */
54*e977b4dbSkenny liang enum {
55*e977b4dbSkenny liang 	WACS_FSM_IDLE            = 0x00,
56*e977b4dbSkenny liang 	WACS_FSM_REQ             = 0x02,
57*e977b4dbSkenny liang 	WACS_FSM_WFDLE           = 0x04,
58*e977b4dbSkenny liang 	WACS_FSM_WFVLDCLR        = 0x06,
59*e977b4dbSkenny liang 	WACS_INIT_DONE           = 0x01,
60*e977b4dbSkenny liang 	WACS_SYNC_IDLE           = 0x01,
61*e977b4dbSkenny liang 	WACS_SYNC_BUSY           = 0x00
62*e977b4dbSkenny liang };
63*e977b4dbSkenny liang 
64*e977b4dbSkenny liang /* error information flag */
65*e977b4dbSkenny liang enum {
66*e977b4dbSkenny liang 	E_PWR_INVALID_ARG             = 1,
67*e977b4dbSkenny liang 	E_PWR_INVALID_RW              = 2,
68*e977b4dbSkenny liang 	E_PWR_INVALID_ADDR            = 3,
69*e977b4dbSkenny liang 	E_PWR_INVALID_WDAT            = 4,
70*e977b4dbSkenny liang 	E_PWR_INVALID_OP_MANUAL       = 5,
71*e977b4dbSkenny liang 	E_PWR_NOT_IDLE_STATE          = 6,
72*e977b4dbSkenny liang 	E_PWR_NOT_INIT_DONE           = 7,
73*e977b4dbSkenny liang 	E_PWR_NOT_INIT_DONE_READ      = 8,
74*e977b4dbSkenny liang 	E_PWR_WAIT_IDLE_TIMEOUT       = 9,
75*e977b4dbSkenny liang 	E_PWR_WAIT_IDLE_TIMEOUT_READ  = 10,
76*e977b4dbSkenny liang 	E_PWR_INIT_SIDLY_FAIL         = 11,
77*e977b4dbSkenny liang 	E_PWR_RESET_TIMEOUT           = 12,
78*e977b4dbSkenny liang 	E_PWR_TIMEOUT                 = 13,
79*e977b4dbSkenny liang 	E_PWR_INIT_RESET_SPI          = 20,
80*e977b4dbSkenny liang 	E_PWR_INIT_SIDLY              = 21,
81*e977b4dbSkenny liang 	E_PWR_INIT_REG_CLOCK          = 22,
82*e977b4dbSkenny liang 	E_PWR_INIT_ENABLE_PMIC        = 23,
83*e977b4dbSkenny liang 	E_PWR_INIT_DIO                = 24,
84*e977b4dbSkenny liang 	E_PWR_INIT_CIPHER             = 25,
85*e977b4dbSkenny liang 	E_PWR_INIT_WRITE_TEST         = 26,
86*e977b4dbSkenny liang 	E_PWR_INIT_ENABLE_CRC         = 27,
87*e977b4dbSkenny liang 	E_PWR_INIT_ENABLE_DEWRAP      = 28,
88*e977b4dbSkenny liang 	E_PWR_INIT_ENABLE_EVENT       = 29,
89*e977b4dbSkenny liang 	E_PWR_READ_TEST_FAIL          = 30,
90*e977b4dbSkenny liang 	E_PWR_WRITE_TEST_FAIL         = 31,
91*e977b4dbSkenny liang 	E_PWR_SWITCH_DIO              = 32
92*e977b4dbSkenny liang };
93*e977b4dbSkenny liang 
94*e977b4dbSkenny liang #endif /* PMIC_WRAP_INIT_H */
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