1 /* 2 * Copyright (c) 2019, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <arch_helpers.h> 9 #include <common/bl_common.h> 10 #include <common/desc_image_load.h> 11 #include <devapc.h> 12 #include <emi_mpu.h> 13 #include <plat/common/common_def.h> 14 #include <drivers/console.h> 15 #include <common/debug.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <mcucfg.h> 18 #include <mt_gic_v3.h> 19 #include <lib/coreboot.h> 20 #include <lib/mmio.h> 21 #include <mtk_mcdi.h> 22 #include <mtk_plat_common.h> 23 #include <mtspmc.h> 24 #include <plat_debug.h> 25 #include <plat_params.h> 26 #include <plat_private.h> 27 #include <platform_def.h> 28 #include <scu.h> 29 #include <spm.h> 30 #include <drivers/ti/uart/uart_16550.h> 31 32 static entry_point_info_t bl32_ep_info; 33 static entry_point_info_t bl33_ep_info; 34 35 static void platform_setup_cpu(void) 36 { 37 mmio_write_32((uintptr_t)&mt8183_mcucfg->mp0_rw_rsvd0, 0x00000001); 38 39 /* Mcusys dcm control */ 40 /* Enable pll plldiv dcm */ 41 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->bus_pll_divider_cfg, 42 BUS_PLLDIV_DCM); 43 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_pll_divider_cfg, 44 MP0_PLLDIV_DCM); 45 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp2_pll_divider_cfg, 46 MP2_PLLDIV_DCM); 47 /* Enable mscib dcm */ 48 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en, 49 MCSIB_CACTIVE_SEL_MASK, MCSIB_CACTIVE_SEL); 50 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en, 51 MCSIB_DCM_MASK, MCSIB_DCM); 52 /* Enable adb400 dcm */ 53 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->cci_adb400_dcm_config, 54 CCI_ADB400_DCM_MASK, CCI_ADB400_DCM); 55 /* Enable bus clock dcm */ 56 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->cci_clk_ctrl, 57 MCU_BUS_DCM); 58 /* Enable bus fabric dcm */ 59 mmio_clrsetbits_32( 60 (uintptr_t)&mt8183_mcucfg->mcusys_bus_fabric_dcm_ctrl, 61 MCUSYS_BUS_FABRIC_DCM_MASK, 62 MCUSYS_BUS_FABRIC_DCM); 63 /* Enable l2c sram dcm */ 64 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->l2c_sram_ctrl, 65 L2C_SRAM_DCM); 66 /* Enable busmp0 sync dcm */ 67 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_config, 68 SYNC_DCM_MASK, SYNC_DCM); 69 /* Enable cntvalue dcm */ 70 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mcu_misc_dcm_ctrl, 71 CNTVALUEB_DCM); 72 /* Enable dcm cluster stall */ 73 mmio_clrsetbits_32( 74 (uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config, 75 MCUSYS_MAX_ACCESS_LATENCY_MASK, 76 MCUSYS_MAX_ACCESS_LATENCY); 77 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config, 78 MCU0_SYNC_DCM_STALL_WR_EN); 79 /* Enable rgu dcm */ 80 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_rgu_dcm_config, 81 CPUSYS_RGU_DCM_CINFIG); 82 } 83 84 /******************************************************************************* 85 * Return a pointer to the 'entry_point_info' structure of the next image for 86 * the security state specified. BL33 corresponds to the non-secure image type 87 * while BL32 corresponds to the secure image type. A NULL pointer is returned 88 * if the image does not exist. 89 ******************************************************************************/ 90 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 91 { 92 entry_point_info_t *next_image_info; 93 94 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 95 assert(next_image_info->h.type == PARAM_EP); 96 97 /* None of the images on this platform can have 0x0 as the entrypoint */ 98 if (next_image_info->pc) 99 return next_image_info; 100 else 101 return NULL; 102 } 103 104 /******************************************************************************* 105 * Perform any BL31 early platform setup. Here is an opportunity to copy 106 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 107 * are lost (potentially). This needs to be done before the MMU is initialized 108 * so that the memory layout can be used while creating page tables. 109 * BL2 has flushed this information to memory, so we are guaranteed to pick up 110 * good data. 111 ******************************************************************************/ 112 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 113 u_register_t arg2, u_register_t arg3) 114 { 115 static console_16550_t console; 116 117 params_early_setup(arg1); 118 119 #if COREBOOT 120 if (coreboot_serial.type) 121 console_16550_register(coreboot_serial.baseaddr, 122 coreboot_serial.input_hertz, 123 coreboot_serial.baud, 124 &console); 125 #else 126 console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console); 127 #endif 128 129 NOTICE("MT8183 bl31_setup\n"); 130 131 bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info); 132 } 133 134 135 /******************************************************************************* 136 * Perform any BL31 platform setup code 137 ******************************************************************************/ 138 void bl31_platform_setup(void) 139 { 140 devapc_init(); 141 142 emi_mpu_init(); 143 144 platform_setup_cpu(); 145 generic_delay_timer_init(); 146 147 /* Initialize the GIC driver, CPU and distributor interfaces */ 148 mt_gic_driver_init(); 149 mt_gic_init(); 150 151 /* Init mcsi SF */ 152 plat_mtk_cci_init_sf(); 153 154 #if SPMC_MODE == 1 155 spmc_init(); 156 #endif 157 spm_boot_init(); 158 mcdi_init(); 159 } 160 161 /******************************************************************************* 162 * Perform the very early platform specific architectural setup here. At the 163 * moment this is only intializes the mmu in a quick and dirty way. 164 ******************************************************************************/ 165 void bl31_plat_arch_setup(void) 166 { 167 plat_mtk_cci_init(); 168 plat_mtk_cci_enable(); 169 170 enable_scu(read_mpidr()); 171 172 plat_configure_mmu_el3(BL_CODE_BASE, 173 BL_COHERENT_RAM_END - BL_CODE_BASE, 174 BL_CODE_BASE, 175 BL_CODE_END, 176 BL_COHERENT_RAM_BASE, 177 BL_COHERENT_RAM_END); 178 } 179