1 /* 2 * Copyright (c) 2019, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <arch_helpers.h> 9 #include <common/bl_common.h> 10 #include <common/desc_image_load.h> 11 #include <plat/common/common_def.h> 12 #include <drivers/console.h> 13 #include <common/debug.h> 14 #include <drivers/generic_delay_timer.h> 15 #include <mcucfg.h> 16 #include <mt_gic_v3.h> 17 #include <lib/coreboot.h> 18 #include <lib/mmio.h> 19 #include <mtk_mcdi.h> 20 #include <mtk_plat_common.h> 21 #include <mtspmc.h> 22 #include <plat_debug.h> 23 #include <plat_params.h> 24 #include <plat_private.h> 25 #include <platform_def.h> 26 #include <scu.h> 27 #include <spm.h> 28 #include <drivers/ti/uart/uart_16550.h> 29 30 static entry_point_info_t bl32_ep_info; 31 static entry_point_info_t bl33_ep_info; 32 33 static void platform_setup_cpu(void) 34 { 35 mmio_write_32((uintptr_t)&mt8183_mcucfg->mp0_rw_rsvd0, 0x00000001); 36 37 /* Mcusys dcm control */ 38 /* Enable pll plldiv dcm */ 39 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->bus_pll_divider_cfg, 40 BUS_PLLDIV_DCM); 41 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_pll_divider_cfg, 42 MP0_PLLDIV_DCM); 43 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp2_pll_divider_cfg, 44 MP2_PLLDIV_DCM); 45 /* Enable mscib dcm */ 46 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en, 47 MCSIB_CACTIVE_SEL_MASK, MCSIB_CACTIVE_SEL); 48 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en, 49 MCSIB_DCM_MASK, MCSIB_DCM); 50 /* Enable adb400 dcm */ 51 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->cci_adb400_dcm_config, 52 CCI_ADB400_DCM_MASK, CCI_ADB400_DCM); 53 /* Enable bus clock dcm */ 54 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->cci_clk_ctrl, 55 MCU_BUS_DCM); 56 /* Enable bus fabric dcm */ 57 mmio_clrsetbits_32( 58 (uintptr_t)&mt8183_mcucfg->mcusys_bus_fabric_dcm_ctrl, 59 MCUSYS_BUS_FABRIC_DCM_MASK, 60 MCUSYS_BUS_FABRIC_DCM); 61 /* Enable l2c sram dcm */ 62 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->l2c_sram_ctrl, 63 L2C_SRAM_DCM); 64 /* Enable busmp0 sync dcm */ 65 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_config, 66 SYNC_DCM_MASK, SYNC_DCM); 67 /* Enable cntvalue dcm */ 68 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mcu_misc_dcm_ctrl, 69 CNTVALUEB_DCM); 70 /* Enable dcm cluster stall */ 71 mmio_clrsetbits_32( 72 (uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config, 73 MCUSYS_MAX_ACCESS_LATENCY_MASK, 74 MCUSYS_MAX_ACCESS_LATENCY); 75 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config, 76 MCU0_SYNC_DCM_STALL_WR_EN); 77 /* Enable rgu dcm */ 78 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_rgu_dcm_config, 79 CPUSYS_RGU_DCM_CINFIG); 80 } 81 82 /******************************************************************************* 83 * Return a pointer to the 'entry_point_info' structure of the next image for 84 * the security state specified. BL33 corresponds to the non-secure image type 85 * while BL32 corresponds to the secure image type. A NULL pointer is returned 86 * if the image does not exist. 87 ******************************************************************************/ 88 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 89 { 90 entry_point_info_t *next_image_info; 91 92 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 93 assert(next_image_info->h.type == PARAM_EP); 94 95 /* None of the images on this platform can have 0x0 as the entrypoint */ 96 if (next_image_info->pc) 97 return next_image_info; 98 else 99 return NULL; 100 } 101 102 /******************************************************************************* 103 * Perform any BL31 early platform setup. Here is an opportunity to copy 104 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 105 * are lost (potentially). This needs to be done before the MMU is initialized 106 * so that the memory layout can be used while creating page tables. 107 * BL2 has flushed this information to memory, so we are guaranteed to pick up 108 * good data. 109 ******************************************************************************/ 110 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 111 u_register_t arg2, u_register_t arg3) 112 { 113 static console_16550_t console; 114 115 params_early_setup(arg1); 116 117 #if COREBOOT 118 if (coreboot_serial.type) 119 console_16550_register(coreboot_serial.baseaddr, 120 coreboot_serial.input_hertz, 121 coreboot_serial.baud, 122 &console); 123 #else 124 console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console); 125 #endif 126 127 NOTICE("MT8183 bl31_setup\n"); 128 129 bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info); 130 } 131 132 133 /******************************************************************************* 134 * Perform any BL31 platform setup code 135 ******************************************************************************/ 136 void bl31_platform_setup(void) 137 { 138 platform_setup_cpu(); 139 generic_delay_timer_init(); 140 141 /* Initialize the GIC driver, CPU and distributor interfaces */ 142 mt_gic_driver_init(); 143 mt_gic_init(); 144 145 /* Init mcsi SF */ 146 plat_mtk_cci_init_sf(); 147 148 #if SPMC_MODE == 1 149 spmc_init(); 150 #endif 151 spm_boot_init(); 152 mcdi_init(); 153 } 154 155 /******************************************************************************* 156 * Perform the very early platform specific architectural setup here. At the 157 * moment this is only intializes the mmu in a quick and dirty way. 158 ******************************************************************************/ 159 void bl31_plat_arch_setup(void) 160 { 161 plat_mtk_cci_init(); 162 plat_mtk_cci_enable(); 163 164 enable_scu(read_mpidr()); 165 166 plat_configure_mmu_el3(BL_CODE_BASE, 167 BL_COHERENT_RAM_END - BL_CODE_BASE, 168 BL_CODE_BASE, 169 BL_CODE_END, 170 BL_COHERENT_RAM_BASE, 171 BL_COHERENT_RAM_END); 172 } 173