1 /* 2 * Copyright (c) 2019, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <arch_helpers.h> 9 #include <common/bl_common.h> 10 #include <common/desc_image_load.h> 11 #include <devapc.h> 12 #include <emi_mpu.h> 13 #include <plat/common/common_def.h> 14 #include <drivers/console.h> 15 #include <common/debug.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <mcucfg.h> 18 #include <mt_gic_v3.h> 19 #include <mt_timer.h> 20 #include <lib/coreboot.h> 21 #include <lib/mmio.h> 22 #include <mtk_mcdi.h> 23 #include <mtk_plat_common.h> 24 #include <mtspmc.h> 25 #include <plat_debug.h> 26 #include <plat_params.h> 27 #include <plat_private.h> 28 #include <platform_def.h> 29 #include <scu.h> 30 #include <spm.h> 31 #include <drivers/ti/uart/uart_16550.h> 32 33 static entry_point_info_t bl32_ep_info; 34 static entry_point_info_t bl33_ep_info; 35 36 static void platform_setup_cpu(void) 37 { 38 mmio_write_32((uintptr_t)&mt8183_mcucfg->mp0_rw_rsvd0, 0x00000001); 39 40 /* Mcusys dcm control */ 41 /* Enable pll plldiv dcm */ 42 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->bus_pll_divider_cfg, 43 BUS_PLLDIV_DCM); 44 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_pll_divider_cfg, 45 MP0_PLLDIV_DCM); 46 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp2_pll_divider_cfg, 47 MP2_PLLDIV_DCM); 48 /* Enable mscib dcm */ 49 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en, 50 MCSIB_CACTIVE_SEL_MASK, MCSIB_CACTIVE_SEL); 51 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en, 52 MCSIB_DCM_MASK, MCSIB_DCM); 53 /* Enable adb400 dcm */ 54 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->cci_adb400_dcm_config, 55 CCI_ADB400_DCM_MASK, CCI_ADB400_DCM); 56 /* Enable bus clock dcm */ 57 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->cci_clk_ctrl, 58 MCU_BUS_DCM); 59 /* Enable bus fabric dcm */ 60 mmio_clrsetbits_32( 61 (uintptr_t)&mt8183_mcucfg->mcusys_bus_fabric_dcm_ctrl, 62 MCUSYS_BUS_FABRIC_DCM_MASK, 63 MCUSYS_BUS_FABRIC_DCM); 64 /* Enable l2c sram dcm */ 65 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->l2c_sram_ctrl, 66 L2C_SRAM_DCM); 67 /* Enable busmp0 sync dcm */ 68 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_config, 69 SYNC_DCM_MASK, SYNC_DCM); 70 /* Enable cntvalue dcm */ 71 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mcu_misc_dcm_ctrl, 72 CNTVALUEB_DCM); 73 /* Enable dcm cluster stall */ 74 mmio_clrsetbits_32( 75 (uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config, 76 MCUSYS_MAX_ACCESS_LATENCY_MASK, 77 MCUSYS_MAX_ACCESS_LATENCY); 78 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config, 79 MCU0_SYNC_DCM_STALL_WR_EN); 80 /* Enable rgu dcm */ 81 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_rgu_dcm_config, 82 CPUSYS_RGU_DCM_CINFIG); 83 } 84 85 /******************************************************************************* 86 * Return a pointer to the 'entry_point_info' structure of the next image for 87 * the security state specified. BL33 corresponds to the non-secure image type 88 * while BL32 corresponds to the secure image type. A NULL pointer is returned 89 * if the image does not exist. 90 ******************************************************************************/ 91 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 92 { 93 entry_point_info_t *next_image_info; 94 95 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 96 assert(next_image_info->h.type == PARAM_EP); 97 98 /* None of the images on this platform can have 0x0 as the entrypoint */ 99 if (next_image_info->pc) 100 return next_image_info; 101 else 102 return NULL; 103 } 104 105 /******************************************************************************* 106 * Perform any BL31 early platform setup. Here is an opportunity to copy 107 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 108 * are lost (potentially). This needs to be done before the MMU is initialized 109 * so that the memory layout can be used while creating page tables. 110 * BL2 has flushed this information to memory, so we are guaranteed to pick up 111 * good data. 112 ******************************************************************************/ 113 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 114 u_register_t arg2, u_register_t arg3) 115 { 116 static console_t console; 117 118 params_early_setup(arg1); 119 120 #if COREBOOT 121 if (coreboot_serial.type) 122 console_16550_register(coreboot_serial.baseaddr, 123 coreboot_serial.input_hertz, 124 coreboot_serial.baud, 125 &console); 126 #else 127 console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console); 128 #endif 129 130 NOTICE("MT8183 bl31_setup\n"); 131 132 bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info); 133 } 134 135 136 /******************************************************************************* 137 * Perform any BL31 platform setup code 138 ******************************************************************************/ 139 void bl31_platform_setup(void) 140 { 141 devapc_init(); 142 143 emi_mpu_init(); 144 145 platform_setup_cpu(); 146 generic_delay_timer_init(); 147 148 /* Initialize the GIC driver, CPU and distributor interfaces */ 149 mt_gic_driver_init(); 150 mt_gic_init(); 151 152 mt_systimer_init(); 153 154 /* Init mcsi SF */ 155 plat_mtk_cci_init_sf(); 156 157 #if SPMC_MODE == 1 158 spmc_init(); 159 #endif 160 spm_boot_init(); 161 mcdi_init(); 162 } 163 164 /******************************************************************************* 165 * Perform the very early platform specific architectural setup here. At the 166 * moment this is only intializes the mmu in a quick and dirty way. 167 ******************************************************************************/ 168 void bl31_plat_arch_setup(void) 169 { 170 plat_mtk_cci_init(); 171 plat_mtk_cci_enable(); 172 173 enable_scu(read_mpidr()); 174 175 plat_configure_mmu_el3(BL_CODE_BASE, 176 BL_COHERENT_RAM_END - BL_CODE_BASE, 177 BL_CODE_BASE, 178 BL_CODE_END, 179 BL_COHERENT_RAM_BASE, 180 BL_COHERENT_RAM_END); 181 } 182