1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <arch_helpers.h> 9 #include <common/bl_common.h> 10 #include <plat/common/common_def.h> 11 #include <drivers/console.h> 12 #include <common/debug.h> 13 #include <drivers/generic_delay_timer.h> 14 #include <mcucfg.h> 15 #include <mt_gic_v3.h> 16 #include <lib/mmio.h> 17 #include <mtk_plat_common.h> 18 #include <plat_debug.h> 19 #include <plat_private.h> 20 #include <platform_def.h> 21 #include <scu.h> 22 #include <drivers/ti/uart/uart_16550.h> 23 24 static entry_point_info_t bl32_ep_info; 25 static entry_point_info_t bl33_ep_info; 26 27 static void platform_setup_cpu(void) 28 { 29 mmio_write_32((uintptr_t)&mt8183_mcucfg->mp0_rw_rsvd0, 0x00000001); 30 31 VERBOSE("addr of cci_adb400_dcm_config: 0x%x\n", 32 mmio_read_32((uintptr_t)&mt8183_mcucfg->cci_adb400_dcm_config)); 33 VERBOSE("addr of sync_dcm_config: 0x%x\n", 34 mmio_read_32((uintptr_t)&mt8183_mcucfg->sync_dcm_config)); 35 36 VERBOSE("mp0_spmc: 0x%x\n", 37 mmio_read_32((uintptr_t)&mt8183_mcucfg->mp0_cputop_spmc_ctl)); 38 VERBOSE("mp1_spmc: 0x%x\n", 39 mmio_read_32((uintptr_t)&mt8183_mcucfg->mp1_cputop_spmc_ctl)); 40 } 41 42 /******************************************************************************* 43 * Return a pointer to the 'entry_point_info' structure of the next image for 44 * the security state specified. BL33 corresponds to the non-secure image type 45 * while BL32 corresponds to the secure image type. A NULL pointer is returned 46 * if the image does not exist. 47 ******************************************************************************/ 48 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 49 { 50 entry_point_info_t *next_image_info; 51 52 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 53 54 /* None of the images on this platform can have 0x0 as the entrypoint */ 55 if (next_image_info->pc) 56 return next_image_info; 57 else 58 return NULL; 59 } 60 61 /******************************************************************************* 62 * Perform any BL31 early platform setup. Here is an opportunity to copy 63 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 64 * are lost (potentially). This needs to be done before the MMU is initialized 65 * so that the memory layout can be used while creating page tables. 66 * BL2 has flushed this information to memory, so we are guaranteed to pick up 67 * good data. 68 ******************************************************************************/ 69 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 70 u_register_t arg2, u_register_t arg3) 71 { 72 struct mtk_bl31_params *arg_from_bl2 = (struct mtk_bl31_params *)arg0; 73 static console_16550_t console; 74 75 console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console); 76 77 NOTICE("MT8183 bl31_setup\n"); 78 79 assert(arg_from_bl2 != NULL); 80 assert(arg_from_bl2->h.type == PARAM_BL31); 81 assert(arg_from_bl2->h.version >= VERSION_1); 82 83 bl32_ep_info = *arg_from_bl2->bl32_ep_info; 84 bl33_ep_info = *arg_from_bl2->bl33_ep_info; 85 } 86 87 88 /******************************************************************************* 89 * Perform any BL31 platform setup code 90 ******************************************************************************/ 91 void bl31_platform_setup(void) 92 { 93 platform_setup_cpu(); 94 generic_delay_timer_init(); 95 96 /* Initialize the GIC driver, CPU and distributor interfaces */ 97 mt_gic_driver_init(); 98 mt_gic_init(); 99 100 /* Init mcsi SF */ 101 plat_mtk_cci_init_sf(); 102 } 103 104 /******************************************************************************* 105 * Perform the very early platform specific architectural setup here. At the 106 * moment this is only intializes the mmu in a quick and dirty way. 107 ******************************************************************************/ 108 void bl31_plat_arch_setup(void) 109 { 110 plat_mtk_cci_init(); 111 plat_mtk_cci_enable(); 112 113 enable_scu(read_mpidr()); 114 115 plat_configure_mmu_el3(BL_CODE_BASE, 116 BL_COHERENT_RAM_END - BL_CODE_BASE, 117 BL_CODE_BASE, 118 BL_CODE_END, 119 BL_COHERENT_RAM_BASE, 120 BL_COHERENT_RAM_END); 121 } 122