1 /* 2 * Copyright (c) 2019, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <arch_helpers.h> 9 #include <common/bl_common.h> 10 #include <common/desc_image_load.h> 11 #include <plat/common/common_def.h> 12 #include <drivers/console.h> 13 #include <common/debug.h> 14 #include <drivers/generic_delay_timer.h> 15 #include <mcucfg.h> 16 #include <mt_gic_v3.h> 17 #include <lib/coreboot.h> 18 #include <lib/mmio.h> 19 #include <mtk_plat_common.h> 20 #include <mtspmc.h> 21 #include <plat_debug.h> 22 #include <plat_params.h> 23 #include <plat_private.h> 24 #include <platform_def.h> 25 #include <scu.h> 26 #include <drivers/ti/uart/uart_16550.h> 27 28 static entry_point_info_t bl32_ep_info; 29 static entry_point_info_t bl33_ep_info; 30 31 static void platform_setup_cpu(void) 32 { 33 mmio_write_32((uintptr_t)&mt8183_mcucfg->mp0_rw_rsvd0, 0x00000001); 34 35 VERBOSE("addr of cci_adb400_dcm_config: 0x%x\n", 36 mmio_read_32((uintptr_t)&mt8183_mcucfg->cci_adb400_dcm_config)); 37 VERBOSE("addr of sync_dcm_config: 0x%x\n", 38 mmio_read_32((uintptr_t)&mt8183_mcucfg->sync_dcm_config)); 39 40 VERBOSE("mp0_spmc: 0x%x\n", 41 mmio_read_32((uintptr_t)&mt8183_mcucfg->mp0_cputop_spmc_ctl)); 42 VERBOSE("mp1_spmc: 0x%x\n", 43 mmio_read_32((uintptr_t)&mt8183_mcucfg->mp1_cputop_spmc_ctl)); 44 } 45 46 /******************************************************************************* 47 * Return a pointer to the 'entry_point_info' structure of the next image for 48 * the security state specified. BL33 corresponds to the non-secure image type 49 * while BL32 corresponds to the secure image type. A NULL pointer is returned 50 * if the image does not exist. 51 ******************************************************************************/ 52 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 53 { 54 entry_point_info_t *next_image_info; 55 56 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 57 assert(next_image_info->h.type == PARAM_EP); 58 59 /* None of the images on this platform can have 0x0 as the entrypoint */ 60 if (next_image_info->pc) 61 return next_image_info; 62 else 63 return NULL; 64 } 65 66 /******************************************************************************* 67 * Perform any BL31 early platform setup. Here is an opportunity to copy 68 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 69 * are lost (potentially). This needs to be done before the MMU is initialized 70 * so that the memory layout can be used while creating page tables. 71 * BL2 has flushed this information to memory, so we are guaranteed to pick up 72 * good data. 73 ******************************************************************************/ 74 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 75 u_register_t arg2, u_register_t arg3) 76 { 77 static console_16550_t console; 78 79 params_early_setup(arg1); 80 81 #if COREBOOT 82 if (coreboot_serial.type) 83 console_16550_register(coreboot_serial.baseaddr, 84 coreboot_serial.input_hertz, 85 coreboot_serial.baud, 86 &console); 87 #else 88 console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console); 89 #endif 90 91 NOTICE("MT8183 bl31_setup\n"); 92 93 bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info); 94 } 95 96 97 /******************************************************************************* 98 * Perform any BL31 platform setup code 99 ******************************************************************************/ 100 void bl31_platform_setup(void) 101 { 102 platform_setup_cpu(); 103 generic_delay_timer_init(); 104 105 /* Initialize the GIC driver, CPU and distributor interfaces */ 106 mt_gic_driver_init(); 107 mt_gic_init(); 108 109 /* Init mcsi SF */ 110 plat_mtk_cci_init_sf(); 111 112 #if SPMC_MODE == 1 113 spmc_init(); 114 #endif 115 } 116 117 /******************************************************************************* 118 * Perform the very early platform specific architectural setup here. At the 119 * moment this is only intializes the mmu in a quick and dirty way. 120 ******************************************************************************/ 121 void bl31_plat_arch_setup(void) 122 { 123 plat_mtk_cci_init(); 124 plat_mtk_cci_enable(); 125 126 enable_scu(read_mpidr()); 127 128 plat_configure_mmu_el3(BL_CODE_BASE, 129 BL_COHERENT_RAM_END - BL_CODE_BASE, 130 BL_CODE_BASE, 131 BL_CODE_END, 132 BL_COHERENT_RAM_BASE, 133 BL_COHERENT_RAM_END); 134 } 135