1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <common/bl_common.h> 9 #include <common/debug.h> 10 #include <mcsi/mcsi.h> 11 #include <platform_def.h> 12 #include <lib/utils.h> 13 #include <lib/xlat_tables/xlat_tables.h> 14 15 static const int cci_map[] = { 16 PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX, 17 PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 18 }; 19 20 /* Table of regions to map using the MMU. */ 21 const mmap_region_t plat_mmap[] = { 22 /* for TF text, RO, RW */ 23 MAP_REGION_FLAT(TZRAM_BASE, TZRAM_SIZE, 24 MT_MEMORY | MT_RW | MT_SECURE), 25 MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE, 26 MT_DEVICE | MT_RW | MT_SECURE), 27 MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE, 28 MT_DEVICE | MT_RW | MT_SECURE), 29 MAP_REGION_FLAT(MTK_DEV_RNG2_BASE, MTK_DEV_RNG2_SIZE, 30 MT_DEVICE | MT_RW | MT_SECURE), 31 { 0 } 32 }; 33 34 /******************************************************************************* 35 * Macro generating the code for the function setting up the pagetables as per 36 * the platform memory map & initialize the mmu, for the given exception level 37 ******************************************************************************/ 38 void plat_configure_mmu_el3(uintptr_t total_base, 39 uintptr_t total_size, 40 uintptr_t ro_start, 41 uintptr_t ro_limit, 42 uintptr_t coh_start, 43 uintptr_t coh_limit) 44 { 45 mmap_add_region(total_base, total_base, total_size, 46 MT_MEMORY | MT_RW | MT_SECURE); 47 mmap_add_region(ro_start, ro_start, ro_limit - ro_start, 48 MT_MEMORY | MT_RO | MT_SECURE); 49 mmap_add_region(coh_start, coh_start, coh_limit - coh_start, 50 MT_DEVICE | MT_RW | MT_SECURE); 51 mmap_add(plat_mmap); 52 init_xlat_tables(); 53 enable_mmu_el3(0); 54 } 55 56 unsigned int plat_get_syscnt_freq2(void) 57 { 58 return SYS_COUNTER_FREQ_IN_TICKS; 59 } 60 61 void plat_mtk_cci_init(void) 62 { 63 /* Initialize CCI driver */ 64 mcsi_init(PLAT_MT_CCI_BASE, ARRAY_SIZE(cci_map)); 65 } 66 67 void plat_mtk_cci_enable(void) 68 { 69 /* Enable CCI coherency for this cluster. 70 * No need for locks as no other cpu is active at the moment. 71 */ 72 cci_enable_cluster_coherency(read_mpidr()); 73 } 74 75 void plat_mtk_cci_disable(void) 76 { 77 cci_disable_cluster_coherency(read_mpidr()); 78 } 79 80 void plat_mtk_cci_init_sf(void) 81 { 82 /* Init mcsi snoop filter. */ 83 cci_init_sf(); 84 } 85