17d116dccSCC Ma /* 27d116dccSCC Ma * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 37d116dccSCC Ma * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 57d116dccSCC Ma */ 67d116dccSCC Ma 77d116dccSCC Ma #include <arch.h> 87d116dccSCC Ma #include <mcucfg.h> 97d116dccSCC Ma #include <mmio.h> 107d116dccSCC Ma 117d116dccSCC Ma void disable_scu(unsigned long mpidr) 127d116dccSCC Ma { 137d116dccSCC Ma if (mpidr & MPIDR_CLUSTER_MASK) 147d116dccSCC Ma mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, 157d116dccSCC Ma MP1_ACINACTM); 167d116dccSCC Ma else 177d116dccSCC Ma mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_axi_config, 187d116dccSCC Ma MP0_ACINACTM); 197d116dccSCC Ma } 207d116dccSCC Ma 217d116dccSCC Ma void enable_scu(unsigned long mpidr) 227d116dccSCC Ma { 237d116dccSCC Ma if (mpidr & MPIDR_CLUSTER_MASK) 247d116dccSCC Ma mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, 257d116dccSCC Ma MP1_ACINACTM); 267d116dccSCC Ma else 277d116dccSCC Ma mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp0_axi_config, 287d116dccSCC Ma MP0_ACINACTM); 297d116dccSCC Ma } 30