1*7d116dccSCC Ma /* 2*7d116dccSCC Ma * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3*7d116dccSCC Ma * 4*7d116dccSCC Ma * Redistribution and use in source and binary forms, with or without 5*7d116dccSCC Ma * modification, are permitted provided that the following conditions are met: 6*7d116dccSCC Ma * 7*7d116dccSCC Ma * Redistributions of source code must retain the above copyright notice, this 8*7d116dccSCC Ma * list of conditions and the following disclaimer. 9*7d116dccSCC Ma * 10*7d116dccSCC Ma * Redistributions in binary form must reproduce the above copyright notice, 11*7d116dccSCC Ma * this list of conditions and the following disclaimer in the documentation 12*7d116dccSCC Ma * and/or other materials provided with the distribution. 13*7d116dccSCC Ma * 14*7d116dccSCC Ma * Neither the name of ARM nor the names of its contributors may be used 15*7d116dccSCC Ma * to endorse or promote products derived from this software without specific 16*7d116dccSCC Ma * prior written permission. 17*7d116dccSCC Ma * 18*7d116dccSCC Ma * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*7d116dccSCC Ma * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*7d116dccSCC Ma * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*7d116dccSCC Ma * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*7d116dccSCC Ma * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*7d116dccSCC Ma * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*7d116dccSCC Ma * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*7d116dccSCC Ma * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*7d116dccSCC Ma * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*7d116dccSCC Ma * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*7d116dccSCC Ma * POSSIBILITY OF SUCH DAMAGE. 29*7d116dccSCC Ma */ 30*7d116dccSCC Ma 31*7d116dccSCC Ma #include <arch.h> 32*7d116dccSCC Ma #include <mcucfg.h> 33*7d116dccSCC Ma #include <mmio.h> 34*7d116dccSCC Ma 35*7d116dccSCC Ma void disable_scu(unsigned long mpidr) 36*7d116dccSCC Ma { 37*7d116dccSCC Ma if (mpidr & MPIDR_CLUSTER_MASK) 38*7d116dccSCC Ma mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, 39*7d116dccSCC Ma MP1_ACINACTM); 40*7d116dccSCC Ma else 41*7d116dccSCC Ma mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_axi_config, 42*7d116dccSCC Ma MP0_ACINACTM); 43*7d116dccSCC Ma } 44*7d116dccSCC Ma 45*7d116dccSCC Ma void enable_scu(unsigned long mpidr) 46*7d116dccSCC Ma { 47*7d116dccSCC Ma if (mpidr & MPIDR_CLUSTER_MASK) 48*7d116dccSCC Ma mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, 49*7d116dccSCC Ma MP1_ACINACTM); 50*7d116dccSCC Ma else 51*7d116dccSCC Ma mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp0_axi_config, 52*7d116dccSCC Ma MP0_ACINACTM); 53*7d116dccSCC Ma } 54