17d116dccSCC Ma /* 27d116dccSCC Ma * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 37d116dccSCC Ma * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 57d116dccSCC Ma */ 67d116dccSCC Ma 77d116dccSCC Ma #include <arch.h> 8*09d40e0eSAntonio Nino Diaz #include <lib/mmio.h> 9*09d40e0eSAntonio Nino Diaz 107d116dccSCC Ma #include <mcucfg.h> 117d116dccSCC Ma disable_scu(unsigned long mpidr)127d116dccSCC Mavoid disable_scu(unsigned long mpidr) 137d116dccSCC Ma { 147d116dccSCC Ma if (mpidr & MPIDR_CLUSTER_MASK) 157d116dccSCC Ma mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, 167d116dccSCC Ma MP1_ACINACTM); 177d116dccSCC Ma else 187d116dccSCC Ma mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_axi_config, 197d116dccSCC Ma MP0_ACINACTM); 207d116dccSCC Ma } 217d116dccSCC Ma enable_scu(unsigned long mpidr)227d116dccSCC Mavoid enable_scu(unsigned long mpidr) 237d116dccSCC Ma { 247d116dccSCC Ma if (mpidr & MPIDR_CLUSTER_MASK) 257d116dccSCC Ma mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, 267d116dccSCC Ma MP1_ACINACTM); 277d116dccSCC Ma else 287d116dccSCC Ma mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp0_axi_config, 297d116dccSCC Ma MP0_ACINACTM); 307d116dccSCC Ma } 31