1*7d116dccSCC Ma /* 2*7d116dccSCC Ma * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3*7d116dccSCC Ma * 4*7d116dccSCC Ma * Redistribution and use in source and binary forms, with or without 5*7d116dccSCC Ma * modification, are permitted provided that the following conditions are met: 6*7d116dccSCC Ma * 7*7d116dccSCC Ma * Redistributions of source code must retain the above copyright notice, this 8*7d116dccSCC Ma * list of conditions and the following disclaimer. 9*7d116dccSCC Ma * 10*7d116dccSCC Ma * Redistributions in binary form must reproduce the above copyright notice, 11*7d116dccSCC Ma * this list of conditions and the following disclaimer in the documentation 12*7d116dccSCC Ma * and/or other materials provided with the distribution. 13*7d116dccSCC Ma * 14*7d116dccSCC Ma * Neither the name of ARM nor the names of its contributors may be used 15*7d116dccSCC Ma * to endorse or promote products derived from this software without specific 16*7d116dccSCC Ma * prior written permission. 17*7d116dccSCC Ma * 18*7d116dccSCC Ma * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*7d116dccSCC Ma * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*7d116dccSCC Ma * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*7d116dccSCC Ma * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*7d116dccSCC Ma * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*7d116dccSCC Ma * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*7d116dccSCC Ma * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*7d116dccSCC Ma * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*7d116dccSCC Ma * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*7d116dccSCC Ma * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*7d116dccSCC Ma * POSSIBILITY OF SUCH DAMAGE. 29*7d116dccSCC Ma */ 30*7d116dccSCC Ma 31*7d116dccSCC Ma #include <arch.h> 32*7d116dccSCC Ma #include <debug.h> 33*7d116dccSCC Ma #include <power_tracer.h> 34*7d116dccSCC Ma 35*7d116dccSCC Ma #define trace_log(...) INFO("psci: " __VA_ARGS__) 36*7d116dccSCC Ma 37*7d116dccSCC Ma void trace_power_flow(unsigned long mpidr, unsigned char mode) 38*7d116dccSCC Ma { 39*7d116dccSCC Ma switch (mode) { 40*7d116dccSCC Ma case CPU_UP: 41*7d116dccSCC Ma trace_log("core %ld:%ld ON\n", 42*7d116dccSCC Ma (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, 43*7d116dccSCC Ma (mpidr & MPIDR_CPU_MASK)); 44*7d116dccSCC Ma break; 45*7d116dccSCC Ma case CPU_DOWN: 46*7d116dccSCC Ma trace_log("core %ld:%ld OFF\n", 47*7d116dccSCC Ma (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, 48*7d116dccSCC Ma (mpidr & MPIDR_CPU_MASK)); 49*7d116dccSCC Ma break; 50*7d116dccSCC Ma case CPU_SUSPEND: 51*7d116dccSCC Ma trace_log("core %ld:%ld SUSPEND\n", 52*7d116dccSCC Ma (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, 53*7d116dccSCC Ma (mpidr & MPIDR_CPU_MASK)); 54*7d116dccSCC Ma break; 55*7d116dccSCC Ma case CLUSTER_UP: 56*7d116dccSCC Ma trace_log("cluster %ld ON\n", 57*7d116dccSCC Ma (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); 58*7d116dccSCC Ma break; 59*7d116dccSCC Ma case CLUSTER_DOWN: 60*7d116dccSCC Ma trace_log("cluster %ld OFF\n", 61*7d116dccSCC Ma (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); 62*7d116dccSCC Ma break; 63*7d116dccSCC Ma case CLUSTER_SUSPEND: 64*7d116dccSCC Ma trace_log("cluster %ld SUSPEND\n", 65*7d116dccSCC Ma (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); 66*7d116dccSCC Ma break; 67*7d116dccSCC Ma default: 68*7d116dccSCC Ma trace_log("unknown power mode\n"); 69*7d116dccSCC Ma break; 70*7d116dccSCC Ma } 71*7d116dccSCC Ma } 72