17d116dccSCC Ma /* 27d116dccSCC Ma * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 37d116dccSCC Ma * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 57d116dccSCC Ma */ 67d116dccSCC Ma 77d116dccSCC Ma #include <arch.h> 87d116dccSCC Ma #include <debug.h> 97d116dccSCC Ma #include <power_tracer.h> 107d116dccSCC Ma 117d116dccSCC Ma #define trace_log(...) INFO("psci: " __VA_ARGS__) 127d116dccSCC Ma 137d116dccSCC Ma void trace_power_flow(unsigned long mpidr, unsigned char mode) 147d116dccSCC Ma { 157d116dccSCC Ma switch (mode) { 167d116dccSCC Ma case CPU_UP: 17*30399885SAntonio Nino Diaz trace_log("core %lld:%lld ON\n", 187d116dccSCC Ma (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, 197d116dccSCC Ma (mpidr & MPIDR_CPU_MASK)); 207d116dccSCC Ma break; 217d116dccSCC Ma case CPU_DOWN: 22*30399885SAntonio Nino Diaz trace_log("core %lld:%lld OFF\n", 237d116dccSCC Ma (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, 247d116dccSCC Ma (mpidr & MPIDR_CPU_MASK)); 257d116dccSCC Ma break; 267d116dccSCC Ma case CPU_SUSPEND: 27*30399885SAntonio Nino Diaz trace_log("core %lld:%lld SUSPEND\n", 287d116dccSCC Ma (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, 297d116dccSCC Ma (mpidr & MPIDR_CPU_MASK)); 307d116dccSCC Ma break; 317d116dccSCC Ma case CLUSTER_UP: 32*30399885SAntonio Nino Diaz trace_log("cluster %lld ON\n", 337d116dccSCC Ma (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); 347d116dccSCC Ma break; 357d116dccSCC Ma case CLUSTER_DOWN: 36*30399885SAntonio Nino Diaz trace_log("cluster %lld OFF\n", 377d116dccSCC Ma (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); 387d116dccSCC Ma break; 397d116dccSCC Ma case CLUSTER_SUSPEND: 40*30399885SAntonio Nino Diaz trace_log("cluster %lld SUSPEND\n", 417d116dccSCC Ma (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); 427d116dccSCC Ma break; 437d116dccSCC Ma default: 447d116dccSCC Ma trace_log("unknown power mode\n"); 457d116dccSCC Ma break; 467d116dccSCC Ma } 477d116dccSCC Ma } 48