xref: /rk3399_ARM-atf/plat/mediatek/mt8173/power_tracer.c (revision 9a207532f8216bf83fed0891fed9ed0bc72ca450)
17d116dccSCC Ma /*
27d116dccSCC Ma  * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
37d116dccSCC Ma  *
482cb2c1aSdp-arm  * SPDX-License-Identifier: BSD-3-Clause
57d116dccSCC Ma  */
67d116dccSCC Ma 
77d116dccSCC Ma #include <arch.h>
8*09d40e0eSAntonio Nino Diaz #include <common/debug.h>
9*09d40e0eSAntonio Nino Diaz 
107d116dccSCC Ma #include <power_tracer.h>
117d116dccSCC Ma 
127d116dccSCC Ma #define trace_log(...)  INFO("psci: " __VA_ARGS__)
137d116dccSCC Ma 
trace_power_flow(unsigned long mpidr,unsigned char mode)147d116dccSCC Ma void trace_power_flow(unsigned long mpidr, unsigned char mode)
157d116dccSCC Ma {
167d116dccSCC Ma 	switch (mode) {
177d116dccSCC Ma 	case CPU_UP:
1830399885SAntonio Nino Diaz 		trace_log("core %lld:%lld ON\n",
197d116dccSCC Ma 			  (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS,
207d116dccSCC Ma 			  (mpidr & MPIDR_CPU_MASK));
217d116dccSCC Ma 		break;
227d116dccSCC Ma 	case CPU_DOWN:
2330399885SAntonio Nino Diaz 		trace_log("core %lld:%lld OFF\n",
247d116dccSCC Ma 			  (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS,
257d116dccSCC Ma 			  (mpidr & MPIDR_CPU_MASK));
267d116dccSCC Ma 		break;
277d116dccSCC Ma 	case CPU_SUSPEND:
2830399885SAntonio Nino Diaz 		trace_log("core %lld:%lld SUSPEND\n",
297d116dccSCC Ma 			  (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS,
307d116dccSCC Ma 			  (mpidr & MPIDR_CPU_MASK));
317d116dccSCC Ma 		break;
327d116dccSCC Ma 	case CLUSTER_UP:
3330399885SAntonio Nino Diaz 		trace_log("cluster %lld ON\n",
347d116dccSCC Ma 			  (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS);
357d116dccSCC Ma 		break;
367d116dccSCC Ma 	case CLUSTER_DOWN:
3730399885SAntonio Nino Diaz 		trace_log("cluster %lld OFF\n",
387d116dccSCC Ma 			  (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS);
397d116dccSCC Ma 		break;
407d116dccSCC Ma 	case CLUSTER_SUSPEND:
4130399885SAntonio Nino Diaz 		trace_log("cluster %lld SUSPEND\n",
427d116dccSCC Ma 			  (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS);
437d116dccSCC Ma 		break;
447d116dccSCC Ma 	default:
457d116dccSCC Ma 		trace_log("unknown power mode\n");
467d116dccSCC Ma 		break;
477d116dccSCC Ma 	}
487d116dccSCC Ma }
49