1*7d116dccSCC Ma /* 2*7d116dccSCC Ma * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. 3*7d116dccSCC Ma * 4*7d116dccSCC Ma * Redistribution and use in source and binary forms, with or without 5*7d116dccSCC Ma * modification, are permitted provided that the following conditions are met: 6*7d116dccSCC Ma * 7*7d116dccSCC Ma * Redistributions of source code must retain the above copyright notice, this 8*7d116dccSCC Ma * list of conditions and the following disclaimer. 9*7d116dccSCC Ma * 10*7d116dccSCC Ma * Redistributions in binary form must reproduce the above copyright notice, 11*7d116dccSCC Ma * this list of conditions and the following disclaimer in the documentation 12*7d116dccSCC Ma * and/or other materials provided with the distribution. 13*7d116dccSCC Ma * 14*7d116dccSCC Ma * Neither the name of ARM nor the names of its contributors may be used 15*7d116dccSCC Ma * to endorse or promote products derived from this software without specific 16*7d116dccSCC Ma * prior written permission. 17*7d116dccSCC Ma * 18*7d116dccSCC Ma * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*7d116dccSCC Ma * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*7d116dccSCC Ma * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*7d116dccSCC Ma * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*7d116dccSCC Ma * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*7d116dccSCC Ma * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*7d116dccSCC Ma * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*7d116dccSCC Ma * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*7d116dccSCC Ma * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*7d116dccSCC Ma * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*7d116dccSCC Ma * POSSIBILITY OF SUCH DAMAGE. 29*7d116dccSCC Ma */ 30*7d116dccSCC Ma #include <arch.h> 31*7d116dccSCC Ma #include <psci.h> 32*7d116dccSCC Ma 33*7d116dccSCC Ma unsigned int plat_get_aff_count(unsigned int aff_lvl, unsigned long mpidr) 34*7d116dccSCC Ma { 35*7d116dccSCC Ma /* Report 1 (absent) instance at levels higher that the cluster level */ 36*7d116dccSCC Ma if (aff_lvl > MPIDR_AFFLVL1) 37*7d116dccSCC Ma return 1; 38*7d116dccSCC Ma 39*7d116dccSCC Ma if (aff_lvl == MPIDR_AFFLVL1) 40*7d116dccSCC Ma return 2; /* We have two clusters */ 41*7d116dccSCC Ma 42*7d116dccSCC Ma return mpidr & 0x100 ? 2 : 2; /* 2 cpus in cluster 1, 2 in cluster 0 */ 43*7d116dccSCC Ma } 44*7d116dccSCC Ma 45*7d116dccSCC Ma unsigned int plat_get_aff_state(unsigned int aff_lvl, unsigned long mpidr) 46*7d116dccSCC Ma { 47*7d116dccSCC Ma return aff_lvl <= MPIDR_AFFLVL2 ? PSCI_AFF_PRESENT : PSCI_AFF_ABSENT; 48*7d116dccSCC Ma } 49*7d116dccSCC Ma 50*7d116dccSCC Ma int mt_setup_topology(void) 51*7d116dccSCC Ma { 52*7d116dccSCC Ma /* [TODO] Make topology configurable via SCC */ 53*7d116dccSCC Ma return 0; 54*7d116dccSCC Ma } 55