xref: /rk3399_ARM-atf/plat/mediatek/mt8173/plat_sip_calls.c (revision b659b1a755a4a73479137ca4b37f55ccba1dbde1)
17d116dccSCC Ma /*
27d116dccSCC Ma  * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
37d116dccSCC Ma  *
47d116dccSCC Ma  * Redistribution and use in source and binary forms, with or without
57d116dccSCC Ma  * modification, are permitted provided that the following conditions are met:
67d116dccSCC Ma  *
77d116dccSCC Ma  * Redistributions of source code must retain the above copyright notice, this
87d116dccSCC Ma  * list of conditions and the following disclaimer.
97d116dccSCC Ma  *
107d116dccSCC Ma  * Redistributions in binary form must reproduce the above copyright notice,
117d116dccSCC Ma  * this list of conditions and the following disclaimer in the documentation
127d116dccSCC Ma  * and/or other materials provided with the distribution.
137d116dccSCC Ma  *
147d116dccSCC Ma  * Neither the name of ARM nor the names of its contributors may be used
157d116dccSCC Ma  * to endorse or promote products derived from this software without specific
167d116dccSCC Ma  * prior written permission.
177d116dccSCC Ma  *
187d116dccSCC Ma  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
197d116dccSCC Ma  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
207d116dccSCC Ma  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
217d116dccSCC Ma  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
227d116dccSCC Ma  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
237d116dccSCC Ma  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
247d116dccSCC Ma  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
257d116dccSCC Ma  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
267d116dccSCC Ma  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
277d116dccSCC Ma  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
287d116dccSCC Ma  * POSSIBILITY OF SUCH DAMAGE.
297d116dccSCC Ma  */
30*b659b1a7SJimmy Huang #include <debug.h>
317d116dccSCC Ma #include <mmio.h>
327d116dccSCC Ma #include <mtk_sip_svc.h>
331a1ff8b9SJimmy Huang #include <mtcmos.h>
34*b659b1a7SJimmy Huang #include <plat_sip_calls.h>
35*b659b1a7SJimmy Huang #include <runtime_svc.h>
367d116dccSCC Ma 
377d116dccSCC Ma /* Authorized secure register list */
387d116dccSCC Ma enum {
397d116dccSCC Ma 	SREG_HDMI_COLOR_EN = 0x14000904
407d116dccSCC Ma };
417d116dccSCC Ma 
427d116dccSCC Ma static const uint32_t authorized_sreg[] = {
437d116dccSCC Ma 	SREG_HDMI_COLOR_EN
447d116dccSCC Ma };
457d116dccSCC Ma 
467d116dccSCC Ma #define authorized_sreg_cnt	\
477d116dccSCC Ma 	(sizeof(authorized_sreg) / sizeof(authorized_sreg[0]))
487d116dccSCC Ma 
497d116dccSCC Ma uint64_t mt_sip_set_authorized_sreg(uint32_t sreg, uint32_t val)
507d116dccSCC Ma {
517d116dccSCC Ma 	uint64_t i;
527d116dccSCC Ma 
537d116dccSCC Ma 	for (i = 0; i < authorized_sreg_cnt; i++) {
547d116dccSCC Ma 		if (authorized_sreg[i] == sreg) {
557d116dccSCC Ma 			mmio_write_32(sreg, val);
567d116dccSCC Ma 			return MTK_SIP_E_SUCCESS;
577d116dccSCC Ma 		}
587d116dccSCC Ma 	}
597d116dccSCC Ma 
607d116dccSCC Ma 	return MTK_SIP_E_INVALID_PARAM;
617d116dccSCC Ma }
621a1ff8b9SJimmy Huang 
63*b659b1a7SJimmy Huang static uint64_t mt_sip_pwr_on_mtcmos(uint32_t val)
641a1ff8b9SJimmy Huang {
651a1ff8b9SJimmy Huang 	uint32_t ret;
661a1ff8b9SJimmy Huang 
671a1ff8b9SJimmy Huang 	ret = mtcmos_non_cpu_ctrl(1, val);
681a1ff8b9SJimmy Huang 	if (ret)
691a1ff8b9SJimmy Huang 		return MTK_SIP_E_INVALID_PARAM;
701a1ff8b9SJimmy Huang 	else
711a1ff8b9SJimmy Huang 		return MTK_SIP_E_SUCCESS;
721a1ff8b9SJimmy Huang }
731a1ff8b9SJimmy Huang 
74*b659b1a7SJimmy Huang static uint64_t mt_sip_pwr_off_mtcmos(uint32_t val)
751a1ff8b9SJimmy Huang {
761a1ff8b9SJimmy Huang 	uint32_t ret;
771a1ff8b9SJimmy Huang 
781a1ff8b9SJimmy Huang 	ret = mtcmos_non_cpu_ctrl(0, val);
791a1ff8b9SJimmy Huang 	if (ret)
801a1ff8b9SJimmy Huang 		return MTK_SIP_E_INVALID_PARAM;
811a1ff8b9SJimmy Huang 	else
821a1ff8b9SJimmy Huang 		return MTK_SIP_E_SUCCESS;
831a1ff8b9SJimmy Huang }
841a1ff8b9SJimmy Huang 
85*b659b1a7SJimmy Huang static uint64_t mt_sip_pwr_mtcmos_support(void)
861a1ff8b9SJimmy Huang {
871a1ff8b9SJimmy Huang 	return MTK_SIP_E_SUCCESS;
881a1ff8b9SJimmy Huang }
89*b659b1a7SJimmy Huang 
90*b659b1a7SJimmy Huang uint64_t mediatek_plat_sip_handler(uint32_t smc_fid,
91*b659b1a7SJimmy Huang 				   uint64_t x1,
92*b659b1a7SJimmy Huang 				   uint64_t x2,
93*b659b1a7SJimmy Huang 				   uint64_t x3,
94*b659b1a7SJimmy Huang 				   uint64_t x4,
95*b659b1a7SJimmy Huang 				   void *cookie,
96*b659b1a7SJimmy Huang 				   void *handle,
97*b659b1a7SJimmy Huang 				   uint64_t flags)
98*b659b1a7SJimmy Huang {
99*b659b1a7SJimmy Huang 	uint64_t ret;
100*b659b1a7SJimmy Huang 
101*b659b1a7SJimmy Huang 	switch (smc_fid) {
102*b659b1a7SJimmy Huang 	case MTK_SIP_PWR_ON_MTCMOS:
103*b659b1a7SJimmy Huang 		ret = mt_sip_pwr_on_mtcmos((uint32_t)x1);
104*b659b1a7SJimmy Huang 		SMC_RET1(handle, ret);
105*b659b1a7SJimmy Huang 
106*b659b1a7SJimmy Huang 	case MTK_SIP_PWR_OFF_MTCMOS:
107*b659b1a7SJimmy Huang 		ret = mt_sip_pwr_off_mtcmos((uint32_t)x1);
108*b659b1a7SJimmy Huang 		SMC_RET1(handle, ret);
109*b659b1a7SJimmy Huang 
110*b659b1a7SJimmy Huang 	case MTK_SIP_PWR_MTCMOS_SUPPORT:
111*b659b1a7SJimmy Huang 		ret = mt_sip_pwr_mtcmos_support();
112*b659b1a7SJimmy Huang 		SMC_RET1(handle, ret);
113*b659b1a7SJimmy Huang 
114*b659b1a7SJimmy Huang 	default:
115*b659b1a7SJimmy Huang 		ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
116*b659b1a7SJimmy Huang 		break;
117*b659b1a7SJimmy Huang 	}
118*b659b1a7SJimmy Huang 
119*b659b1a7SJimmy Huang 	SMC_RET1(handle, SMC_UNK);
120*b659b1a7SJimmy Huang }
121