17d116dccSCC Ma /* 27d116dccSCC Ma * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 37d116dccSCC Ma * 47d116dccSCC Ma * Redistribution and use in source and binary forms, with or without 57d116dccSCC Ma * modification, are permitted provided that the following conditions are met: 67d116dccSCC Ma * 77d116dccSCC Ma * Redistributions of source code must retain the above copyright notice, this 87d116dccSCC Ma * list of conditions and the following disclaimer. 97d116dccSCC Ma * 107d116dccSCC Ma * Redistributions in binary form must reproduce the above copyright notice, 117d116dccSCC Ma * this list of conditions and the following disclaimer in the documentation 127d116dccSCC Ma * and/or other materials provided with the distribution. 137d116dccSCC Ma * 147d116dccSCC Ma * Neither the name of ARM nor the names of its contributors may be used 157d116dccSCC Ma * to endorse or promote products derived from this software without specific 167d116dccSCC Ma * prior written permission. 177d116dccSCC Ma * 187d116dccSCC Ma * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 197d116dccSCC Ma * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 207d116dccSCC Ma * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 217d116dccSCC Ma * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 227d116dccSCC Ma * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 237d116dccSCC Ma * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 247d116dccSCC Ma * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 257d116dccSCC Ma * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 267d116dccSCC Ma * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 277d116dccSCC Ma * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 287d116dccSCC Ma * POSSIBILITY OF SUCH DAMAGE. 297d116dccSCC Ma */ 30*7ace1cc0SYi Zheng #include <crypt.h> 31b659b1a7SJimmy Huang #include <debug.h> 327d116dccSCC Ma #include <mmio.h> 337d116dccSCC Ma #include <mtk_sip_svc.h> 341a1ff8b9SJimmy Huang #include <mtcmos.h> 35b659b1a7SJimmy Huang #include <plat_sip_calls.h> 36b659b1a7SJimmy Huang #include <runtime_svc.h> 377d116dccSCC Ma 387d116dccSCC Ma /* Authorized secure register list */ 397d116dccSCC Ma enum { 407d116dccSCC Ma SREG_HDMI_COLOR_EN = 0x14000904 417d116dccSCC Ma }; 427d116dccSCC Ma 437d116dccSCC Ma static const uint32_t authorized_sreg[] = { 447d116dccSCC Ma SREG_HDMI_COLOR_EN 457d116dccSCC Ma }; 467d116dccSCC Ma 477d116dccSCC Ma #define authorized_sreg_cnt \ 487d116dccSCC Ma (sizeof(authorized_sreg) / sizeof(authorized_sreg[0])) 497d116dccSCC Ma 507d116dccSCC Ma uint64_t mt_sip_set_authorized_sreg(uint32_t sreg, uint32_t val) 517d116dccSCC Ma { 527d116dccSCC Ma uint64_t i; 537d116dccSCC Ma 547d116dccSCC Ma for (i = 0; i < authorized_sreg_cnt; i++) { 557d116dccSCC Ma if (authorized_sreg[i] == sreg) { 567d116dccSCC Ma mmio_write_32(sreg, val); 577d116dccSCC Ma return MTK_SIP_E_SUCCESS; 587d116dccSCC Ma } 597d116dccSCC Ma } 607d116dccSCC Ma 617d116dccSCC Ma return MTK_SIP_E_INVALID_PARAM; 627d116dccSCC Ma } 631a1ff8b9SJimmy Huang 64b659b1a7SJimmy Huang static uint64_t mt_sip_pwr_on_mtcmos(uint32_t val) 651a1ff8b9SJimmy Huang { 661a1ff8b9SJimmy Huang uint32_t ret; 671a1ff8b9SJimmy Huang 681a1ff8b9SJimmy Huang ret = mtcmos_non_cpu_ctrl(1, val); 691a1ff8b9SJimmy Huang if (ret) 701a1ff8b9SJimmy Huang return MTK_SIP_E_INVALID_PARAM; 711a1ff8b9SJimmy Huang else 721a1ff8b9SJimmy Huang return MTK_SIP_E_SUCCESS; 731a1ff8b9SJimmy Huang } 741a1ff8b9SJimmy Huang 75b659b1a7SJimmy Huang static uint64_t mt_sip_pwr_off_mtcmos(uint32_t val) 761a1ff8b9SJimmy Huang { 771a1ff8b9SJimmy Huang uint32_t ret; 781a1ff8b9SJimmy Huang 791a1ff8b9SJimmy Huang ret = mtcmos_non_cpu_ctrl(0, val); 801a1ff8b9SJimmy Huang if (ret) 811a1ff8b9SJimmy Huang return MTK_SIP_E_INVALID_PARAM; 821a1ff8b9SJimmy Huang else 831a1ff8b9SJimmy Huang return MTK_SIP_E_SUCCESS; 841a1ff8b9SJimmy Huang } 851a1ff8b9SJimmy Huang 86b659b1a7SJimmy Huang static uint64_t mt_sip_pwr_mtcmos_support(void) 871a1ff8b9SJimmy Huang { 881a1ff8b9SJimmy Huang return MTK_SIP_E_SUCCESS; 891a1ff8b9SJimmy Huang } 90b659b1a7SJimmy Huang 91b659b1a7SJimmy Huang uint64_t mediatek_plat_sip_handler(uint32_t smc_fid, 92b659b1a7SJimmy Huang uint64_t x1, 93b659b1a7SJimmy Huang uint64_t x2, 94b659b1a7SJimmy Huang uint64_t x3, 95b659b1a7SJimmy Huang uint64_t x4, 96b659b1a7SJimmy Huang void *cookie, 97b659b1a7SJimmy Huang void *handle, 98b659b1a7SJimmy Huang uint64_t flags) 99b659b1a7SJimmy Huang { 100b659b1a7SJimmy Huang uint64_t ret; 101b659b1a7SJimmy Huang 102b659b1a7SJimmy Huang switch (smc_fid) { 103b659b1a7SJimmy Huang case MTK_SIP_PWR_ON_MTCMOS: 104b659b1a7SJimmy Huang ret = mt_sip_pwr_on_mtcmos((uint32_t)x1); 105b659b1a7SJimmy Huang SMC_RET1(handle, ret); 106b659b1a7SJimmy Huang 107b659b1a7SJimmy Huang case MTK_SIP_PWR_OFF_MTCMOS: 108b659b1a7SJimmy Huang ret = mt_sip_pwr_off_mtcmos((uint32_t)x1); 109b659b1a7SJimmy Huang SMC_RET1(handle, ret); 110b659b1a7SJimmy Huang 111b659b1a7SJimmy Huang case MTK_SIP_PWR_MTCMOS_SUPPORT: 112b659b1a7SJimmy Huang ret = mt_sip_pwr_mtcmos_support(); 113b659b1a7SJimmy Huang SMC_RET1(handle, ret); 114b659b1a7SJimmy Huang 115*7ace1cc0SYi Zheng case MTK_SIP_SET_HDCP_KEY_EX: 116*7ace1cc0SYi Zheng ret = crypt_set_hdcp_key_ex(x1, x2, x3); 117*7ace1cc0SYi Zheng SMC_RET1(handle, ret); 118*7ace1cc0SYi Zheng 119*7ace1cc0SYi Zheng case MTK_SIP_SET_HDCP_KEY_NUM: 120*7ace1cc0SYi Zheng ret = crypt_set_hdcp_key_num((uint32_t)x1); 121*7ace1cc0SYi Zheng SMC_RET1(handle, ret); 122*7ace1cc0SYi Zheng 123*7ace1cc0SYi Zheng case MTK_SIP_CLR_HDCP_KEY: 124*7ace1cc0SYi Zheng ret = crypt_clear_hdcp_key(); 125*7ace1cc0SYi Zheng SMC_RET1(handle, ret); 126*7ace1cc0SYi Zheng 127b659b1a7SJimmy Huang default: 128b659b1a7SJimmy Huang ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 129b659b1a7SJimmy Huang break; 130b659b1a7SJimmy Huang } 131b659b1a7SJimmy Huang 132b659b1a7SJimmy Huang SMC_RET1(handle, SMC_UNK); 133b659b1a7SJimmy Huang } 134