xref: /rk3399_ARM-atf/plat/mediatek/mt8173/plat_sip_calls.c (revision 1e81e9a4c7d96df1fc0edafb5b332aab0b61932d)
17d116dccSCC Ma /*
27d116dccSCC Ma  * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
37d116dccSCC Ma  *
482cb2c1aSdp-arm  * SPDX-License-Identifier: BSD-3-Clause
57d116dccSCC Ma  */
609d40e0eSAntonio Nino Diaz 
709d40e0eSAntonio Nino Diaz #include <common/debug.h>
809d40e0eSAntonio Nino Diaz #include <common/runtime_svc.h>
909d40e0eSAntonio Nino Diaz #include <lib/mmio.h>
1009d40e0eSAntonio Nino Diaz 
117ace1cc0SYi Zheng #include <crypt.h>
121a1ff8b9SJimmy Huang #include <mtcmos.h>
13ee1ebbd1SIsla Mitchell #include <mtk_sip_svc.h>
14b659b1a7SJimmy Huang #include <plat_sip_calls.h>
15*e9cf1bccSJulius Werner #include <wdt.h>
167d116dccSCC Ma 
177d116dccSCC Ma /* Authorized secure register list */
187d116dccSCC Ma enum {
197d116dccSCC Ma 	SREG_HDMI_COLOR_EN = 0x14000904
207d116dccSCC Ma };
217d116dccSCC Ma 
227d116dccSCC Ma static const uint32_t authorized_sreg[] = {
237d116dccSCC Ma 	SREG_HDMI_COLOR_EN
247d116dccSCC Ma };
257d116dccSCC Ma 
267d116dccSCC Ma #define authorized_sreg_cnt	\
277d116dccSCC Ma 	(sizeof(authorized_sreg) / sizeof(authorized_sreg[0]))
287d116dccSCC Ma 
mt_sip_set_authorized_sreg(uint32_t sreg,uint32_t val)297d116dccSCC Ma uint64_t mt_sip_set_authorized_sreg(uint32_t sreg, uint32_t val)
307d116dccSCC Ma {
317d116dccSCC Ma 	uint64_t i;
327d116dccSCC Ma 
337d116dccSCC Ma 	for (i = 0; i < authorized_sreg_cnt; i++) {
347d116dccSCC Ma 		if (authorized_sreg[i] == sreg) {
357d116dccSCC Ma 			mmio_write_32(sreg, val);
367d116dccSCC Ma 			return MTK_SIP_E_SUCCESS;
377d116dccSCC Ma 		}
387d116dccSCC Ma 	}
397d116dccSCC Ma 
407d116dccSCC Ma 	return MTK_SIP_E_INVALID_PARAM;
417d116dccSCC Ma }
421a1ff8b9SJimmy Huang 
mt_sip_pwr_on_mtcmos(uint32_t val)43b659b1a7SJimmy Huang static uint64_t mt_sip_pwr_on_mtcmos(uint32_t val)
441a1ff8b9SJimmy Huang {
451a1ff8b9SJimmy Huang 	uint32_t ret;
461a1ff8b9SJimmy Huang 
471a1ff8b9SJimmy Huang 	ret = mtcmos_non_cpu_ctrl(1, val);
481a1ff8b9SJimmy Huang 	if (ret)
491a1ff8b9SJimmy Huang 		return MTK_SIP_E_INVALID_PARAM;
501a1ff8b9SJimmy Huang 	else
511a1ff8b9SJimmy Huang 		return MTK_SIP_E_SUCCESS;
521a1ff8b9SJimmy Huang }
531a1ff8b9SJimmy Huang 
mt_sip_pwr_off_mtcmos(uint32_t val)54b659b1a7SJimmy Huang static uint64_t mt_sip_pwr_off_mtcmos(uint32_t val)
551a1ff8b9SJimmy Huang {
561a1ff8b9SJimmy Huang 	uint32_t ret;
571a1ff8b9SJimmy Huang 
581a1ff8b9SJimmy Huang 	ret = mtcmos_non_cpu_ctrl(0, val);
591a1ff8b9SJimmy Huang 	if (ret)
601a1ff8b9SJimmy Huang 		return MTK_SIP_E_INVALID_PARAM;
611a1ff8b9SJimmy Huang 	else
621a1ff8b9SJimmy Huang 		return MTK_SIP_E_SUCCESS;
631a1ff8b9SJimmy Huang }
641a1ff8b9SJimmy Huang 
mt_sip_pwr_mtcmos_support(void)65b659b1a7SJimmy Huang static uint64_t mt_sip_pwr_mtcmos_support(void)
661a1ff8b9SJimmy Huang {
671a1ff8b9SJimmy Huang 	return MTK_SIP_E_SUCCESS;
681a1ff8b9SJimmy Huang }
69b659b1a7SJimmy Huang 
mediatek_plat_sip_handler(uint32_t smc_fid,uint64_t x1,uint64_t x2,uint64_t x3,uint64_t x4,void * cookie,void * handle,uint64_t flags)70b659b1a7SJimmy Huang uint64_t mediatek_plat_sip_handler(uint32_t smc_fid,
71b659b1a7SJimmy Huang 				   uint64_t x1,
72b659b1a7SJimmy Huang 				   uint64_t x2,
73b659b1a7SJimmy Huang 				   uint64_t x3,
74b659b1a7SJimmy Huang 				   uint64_t x4,
75b659b1a7SJimmy Huang 				   void *cookie,
76b659b1a7SJimmy Huang 				   void *handle,
77b659b1a7SJimmy Huang 				   uint64_t flags)
78b659b1a7SJimmy Huang {
79b659b1a7SJimmy Huang 	uint64_t ret;
80b659b1a7SJimmy Huang 
81b659b1a7SJimmy Huang 	switch (smc_fid) {
82b659b1a7SJimmy Huang 	case MTK_SIP_PWR_ON_MTCMOS:
83b659b1a7SJimmy Huang 		ret = mt_sip_pwr_on_mtcmos((uint32_t)x1);
84b659b1a7SJimmy Huang 		SMC_RET1(handle, ret);
85b659b1a7SJimmy Huang 
86b659b1a7SJimmy Huang 	case MTK_SIP_PWR_OFF_MTCMOS:
87b659b1a7SJimmy Huang 		ret = mt_sip_pwr_off_mtcmos((uint32_t)x1);
88b659b1a7SJimmy Huang 		SMC_RET1(handle, ret);
89b659b1a7SJimmy Huang 
90b659b1a7SJimmy Huang 	case MTK_SIP_PWR_MTCMOS_SUPPORT:
91b659b1a7SJimmy Huang 		ret = mt_sip_pwr_mtcmos_support();
92b659b1a7SJimmy Huang 		SMC_RET1(handle, ret);
93b659b1a7SJimmy Huang 
947ace1cc0SYi Zheng 	case MTK_SIP_SET_HDCP_KEY_EX:
957ace1cc0SYi Zheng 		ret = crypt_set_hdcp_key_ex(x1, x2, x3);
967ace1cc0SYi Zheng 		SMC_RET1(handle, ret);
977ace1cc0SYi Zheng 
987ace1cc0SYi Zheng 	case MTK_SIP_SET_HDCP_KEY_NUM:
997ace1cc0SYi Zheng 		ret = crypt_set_hdcp_key_num((uint32_t)x1);
1007ace1cc0SYi Zheng 		SMC_RET1(handle, ret);
1017ace1cc0SYi Zheng 
1027ace1cc0SYi Zheng 	case MTK_SIP_CLR_HDCP_KEY:
1037ace1cc0SYi Zheng 		ret = crypt_clear_hdcp_key();
1047ace1cc0SYi Zheng 		SMC_RET1(handle, ret);
1057ace1cc0SYi Zheng 
106*e9cf1bccSJulius Werner 	case MTK_SIP_SMC_WATCHDOG:
107*e9cf1bccSJulius Werner 		return wdt_smc_handler(x1, x2, handle);
108*e9cf1bccSJulius Werner 
109b659b1a7SJimmy Huang 	default:
110b659b1a7SJimmy Huang 		ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
111b659b1a7SJimmy Huang 		break;
112b659b1a7SJimmy Huang 	}
113b659b1a7SJimmy Huang 
114b659b1a7SJimmy Huang 	SMC_RET1(handle, SMC_UNK);
115b659b1a7SJimmy Huang }
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