1 /* 2 * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PLATFORM_DEF_H__ 32 #define __PLATFORM_DEF_H__ 33 34 #define DEBUG_XLAT_TABLE 0 35 36 /******************************************************************************* 37 * Platform binary types for linking 38 ******************************************************************************/ 39 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 40 #define PLATFORM_LINKER_ARCH aarch64 41 42 /******************************************************************************* 43 * Generic platform constants 44 ******************************************************************************/ 45 46 /* Size of cacheable stacks */ 47 #if DEBUG_XLAT_TABLE 48 #define PLATFORM_STACK_SIZE 0x800 49 #elif IMAGE_BL1 50 #define PLATFORM_STACK_SIZE 0x440 51 #elif IMAGE_BL2 52 #define PLATFORM_STACK_SIZE 0x400 53 #elif IMAGE_BL31 54 #define PLATFORM_STACK_SIZE 0x800 55 #elif IMAGE_BL32 56 #define PLATFORM_STACK_SIZE 0x440 57 #endif 58 59 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 60 61 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 62 #define PLATFORM_SYSTEM_COUNT 1 63 #define PLATFORM_CLUSTER_COUNT 2 64 #define PLATFORM_CLUSTER0_CORE_COUNT 4 65 #define PLATFORM_CLUSTER1_CORE_COUNT 2 66 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 67 PLATFORM_CLUSTER0_CORE_COUNT) 68 #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 69 #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 70 PLATFORM_CLUSTER_COUNT + \ 71 PLATFORM_CORE_COUNT) 72 73 /******************************************************************************* 74 * Platform memory map related constants 75 ******************************************************************************/ 76 /* TF txet, ro, rw, internal SRAM, Size: release: 80KB, debug: 92KB */ 77 #define TZRAM_BASE (0x100000) 78 #if DEBUG 79 #define TZRAM_SIZE (0x20000) 80 #else 81 #define TZRAM_SIZE (0x20000) 82 #endif 83 84 /* xlat_table , coherence ram, 64KB */ 85 #define TZRAM2_BASE (TZRAM_BASE + TZRAM_SIZE) 86 #define TZRAM2_SIZE (0x10000) 87 88 /******************************************************************************* 89 * BL31 specific defines. 90 ******************************************************************************/ 91 /* 92 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 93 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 94 * little space for growth. 95 */ 96 #define BL31_BASE (TZRAM_BASE + 0x1000) 97 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 98 #define TZRAM2_LIMIT (TZRAM2_BASE + TZRAM2_SIZE) 99 100 /******************************************************************************* 101 * Platform specific page table and MMU setup constants 102 ******************************************************************************/ 103 #define ADDR_SPACE_SIZE (1ull << 32) 104 #define MAX_XLAT_TABLES 4 105 #define MAX_MMAP_REGIONS 16 106 107 /******************************************************************************* 108 * Declarations and constants to access the mailboxes safely. Each mailbox is 109 * aligned on the biggest cache line size in the platform. This is known only 110 * to the platform as it might have a combination of integrated and external 111 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 112 * line at any cache level. They could belong to different cpus/clusters & 113 * get written while being protected by different locks causing corruption of 114 * a valid mailbox address. 115 ******************************************************************************/ 116 #define CACHE_WRITEBACK_SHIFT 6 117 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 118 119 #endif /* __PLATFORM_DEF_H__ */ 120