1 /* 2 * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PLATFORM_DEF_H__ 32 #define __PLATFORM_DEF_H__ 33 34 #include "mt8173_def.h" 35 36 37 /******************************************************************************* 38 * Platform binary types for linking 39 ******************************************************************************/ 40 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 41 #define PLATFORM_LINKER_ARCH aarch64 42 43 /******************************************************************************* 44 * Generic platform constants 45 ******************************************************************************/ 46 47 /* Size of cacheable stacks */ 48 #if defined(IMAGE_BL1) 49 #define PLATFORM_STACK_SIZE 0x440 50 #elif defined(IMAGE_BL2) 51 #define PLATFORM_STACK_SIZE 0x400 52 #elif defined(IMAGE_BL31) 53 #define PLATFORM_STACK_SIZE 0x800 54 #elif defined(IMAGE_BL32) 55 #define PLATFORM_STACK_SIZE 0x440 56 #endif 57 58 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 59 60 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 61 #if !ENABLE_PLAT_COMPAT 62 #define PLAT_MAX_PWR_LVL 2 63 #define PLAT_MAX_RET_STATE 1 64 #define PLAT_MAX_OFF_STATE 2 65 #endif 66 #define PLATFORM_SYSTEM_COUNT 1 67 #define PLATFORM_CLUSTER_COUNT 2 68 #define PLATFORM_CLUSTER0_CORE_COUNT 4 69 #define PLATFORM_CLUSTER1_CORE_COUNT 2 70 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 71 PLATFORM_CLUSTER0_CORE_COUNT) 72 #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 73 #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 74 PLATFORM_CLUSTER_COUNT + \ 75 PLATFORM_CORE_COUNT) 76 77 /******************************************************************************* 78 * Platform memory map related constants 79 ******************************************************************************/ 80 /* 81 * MT8173 SRAM memory layout 82 * 0x100000 +-------------------+ 83 * | shared mem (4KB) | 84 * 0x101000 +-------------------+ 85 * | | 86 * | BL3-1 (124KB) | 87 * | | 88 * 0x120000 +-------------------+ 89 * | reserved (64KB) | 90 * 0x130000 +-------------------+ 91 */ 92 /* TF txet, ro, rw, xlat table, coherent memory ... etc. 93 * Size: release: 128KB, debug: 128KB 94 */ 95 #define TZRAM_BASE (0x100000) 96 #if DEBUG 97 #define TZRAM_SIZE (0x20000) 98 #else 99 #define TZRAM_SIZE (0x20000) 100 #endif 101 102 /* Reserved: 64KB */ 103 #define TZRAM2_BASE (TZRAM_BASE + TZRAM_SIZE) 104 #define TZRAM2_SIZE (0x10000) 105 106 /******************************************************************************* 107 * BL31 specific defines. 108 ******************************************************************************/ 109 /* 110 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 111 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 112 * little space for growth. 113 */ 114 #define BL31_BASE (TZRAM_BASE + 0x1000) 115 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 116 #define TZRAM2_LIMIT (TZRAM2_BASE + TZRAM2_SIZE) 117 118 /******************************************************************************* 119 * Platform specific page table and MMU setup constants 120 ******************************************************************************/ 121 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 122 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 123 #define MAX_XLAT_TABLES 4 124 #define MAX_MMAP_REGIONS 16 125 126 /******************************************************************************* 127 * Declarations and constants to access the mailboxes safely. Each mailbox is 128 * aligned on the biggest cache line size in the platform. This is known only 129 * to the platform as it might have a combination of integrated and external 130 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 131 * line at any cache level. They could belong to different cpus/clusters & 132 * get written while being protected by different locks causing corruption of 133 * a valid mailbox address. 134 ******************************************************************************/ 135 #define CACHE_WRITEBACK_SHIFT 6 136 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 137 138 139 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 140 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 141 142 #define PLAT_ARM_G1S_IRQS MT_IRQ_SEC_SGI_0, \ 143 MT_IRQ_SEC_SGI_1, \ 144 MT_IRQ_SEC_SGI_2, \ 145 MT_IRQ_SEC_SGI_3, \ 146 MT_IRQ_SEC_SGI_4, \ 147 MT_IRQ_SEC_SGI_5, \ 148 MT_IRQ_SEC_SGI_6, \ 149 MT_IRQ_SEC_SGI_7 150 151 #define PLAT_ARM_G0_IRQS 152 153 #endif /* __PLATFORM_DEF_H__ */ 154