1 /* 2 * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PLATFORM_DEF_H__ 32 #define __PLATFORM_DEF_H__ 33 34 35 /******************************************************************************* 36 * Platform binary types for linking 37 ******************************************************************************/ 38 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 39 #define PLATFORM_LINKER_ARCH aarch64 40 41 /******************************************************************************* 42 * Generic platform constants 43 ******************************************************************************/ 44 45 /* Size of cacheable stacks */ 46 #if IMAGE_BL1 47 #define PLATFORM_STACK_SIZE 0x440 48 #elif IMAGE_BL2 49 #define PLATFORM_STACK_SIZE 0x400 50 #elif IMAGE_BL31 51 #define PLATFORM_STACK_SIZE 0x800 52 #elif IMAGE_BL32 53 #define PLATFORM_STACK_SIZE 0x440 54 #endif 55 56 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 57 58 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 59 #define PLATFORM_SYSTEM_COUNT 1 60 #define PLATFORM_CLUSTER_COUNT 2 61 #define PLATFORM_CLUSTER0_CORE_COUNT 4 62 #define PLATFORM_CLUSTER1_CORE_COUNT 2 63 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 64 PLATFORM_CLUSTER0_CORE_COUNT) 65 #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 66 #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 67 PLATFORM_CLUSTER_COUNT + \ 68 PLATFORM_CORE_COUNT) 69 70 /******************************************************************************* 71 * Platform memory map related constants 72 ******************************************************************************/ 73 /* TF txet, ro, rw, internal SRAM, Size: release: 80KB, debug: 92KB */ 74 #define TZRAM_BASE (0x100000) 75 #if DEBUG 76 #define TZRAM_SIZE (0x20000) 77 #else 78 #define TZRAM_SIZE (0x20000) 79 #endif 80 81 /* xlat_table , coherence ram, 64KB */ 82 #define TZRAM2_BASE (TZRAM_BASE + TZRAM_SIZE) 83 #define TZRAM2_SIZE (0x10000) 84 85 /******************************************************************************* 86 * BL31 specific defines. 87 ******************************************************************************/ 88 /* 89 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 90 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 91 * little space for growth. 92 */ 93 #define BL31_BASE (TZRAM_BASE + 0x1000) 94 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 95 #define TZRAM2_LIMIT (TZRAM2_BASE + TZRAM2_SIZE) 96 97 /******************************************************************************* 98 * Platform specific page table and MMU setup constants 99 ******************************************************************************/ 100 #define ADDR_SPACE_SIZE (1ull << 32) 101 #define MAX_XLAT_TABLES 4 102 #define MAX_MMAP_REGIONS 16 103 104 /******************************************************************************* 105 * Declarations and constants to access the mailboxes safely. Each mailbox is 106 * aligned on the biggest cache line size in the platform. This is known only 107 * to the platform as it might have a combination of integrated and external 108 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 109 * line at any cache level. They could belong to different cpus/clusters & 110 * get written while being protected by different locks causing corruption of 111 * a valid mailbox address. 112 ******************************************************************************/ 113 #define CACHE_WRITEBACK_SHIFT 6 114 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 115 116 #endif /* __PLATFORM_DEF_H__ */ 117