1/* 2 * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <cci.h> 32#include <gic_common.h> 33#include <gicv2.h> 34#include <mt8173_def.h> 35 36.section .rodata.gic_reg_name, "aS" 37gicc_regs: 38 .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 39gicd_pend_reg: 40 .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \ 41 " Offset:\t\t\tvalue\n" 42newline: 43 .asciz "\n" 44spacer: 45 .asciz ":\t\t0x" 46 47.section .rodata.cci_reg_name, "aS" 48cci_iface_regs: 49 .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" 50 51 /* --------------------------------------------- 52 * The below macro prints out relevant GIC and 53 * CCI registers whenever an unhandled exception 54 * is taken in BL3-1. 55 * Clobbers: x0 - x10, x16, x17, sp 56 * --------------------------------------------- 57 */ 58 .macro plat_crash_print_regs 59 mov_imm x16, BASE_GICD_BASE 60 mov_imm x17, BASE_GICC_BASE 61 /* Load the gicc reg list to x6 */ 62 adr x6, gicc_regs 63 /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 64 ldr w8, [x17, #GICC_HPPIR] 65 ldr w9, [x17, #GICC_AHPPIR] 66 ldr w10, [x17, #GICC_CTLR] 67 /* Store to the crash buf and print to console */ 68 bl str_in_crash_buf_print 69 70 /* Print the GICD_ISPENDR regs */ 71 add x7, x16, #GICD_ISPENDR 72 adr x4, gicd_pend_reg 73 bl asm_print_str 74gicd_ispendr_loop: 75 sub x4, x7, x16 76 cmp x4, #0x280 77 b.eq exit_print_gic_regs 78 bl asm_print_hex 79 80 adr x4, spacer 81 bl asm_print_str 82 83 ldr x4, [x7], #8 84 bl asm_print_hex 85 86 adr x4, newline 87 bl asm_print_str 88 b gicd_ispendr_loop 89exit_print_gic_regs: 90 91 adr x6, cci_iface_regs 92 /* Store in x7 the base address of the first interface */ 93 mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \ 94 PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX)) 95 ldr w8, [x7, #SNOOP_CTRL_REG] 96 /* Store in x7 the base address of the second interface */ 97 mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \ 98 PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX)) 99 ldr w9, [x7, #SNOOP_CTRL_REG] 100 /* Store to the crash buf and print to console */ 101 bl str_in_crash_buf_print 102 .endm 103