1 /* 2 * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __MT8173_DEF_H__ 32 #define __MT8173_DEF_H__ 33 34 #if RESET_TO_BL31 35 #error "MT8173 is incompatible with RESET_TO_BL31!" 36 #endif 37 38 #define MT8173_PRIMARY_CPU 0x0 39 40 /* Register base address */ 41 #define IO_PHYS (0x10000000) 42 #define INFRACFG_AO_BASE (IO_PHYS + 0x1000) 43 #define PERI_CON_BASE (IO_PHYS + 0x3000) 44 #define GPIO_BASE (IO_PHYS + 0x5000) 45 #define SPM_BASE (IO_PHYS + 0x6000) 46 #define RGU_BASE (IO_PHYS + 0x7000) 47 #define PMIC_WRAP_BASE (IO_PHYS + 0xD000) 48 #define MCUCFG_BASE (IO_PHYS + 0x200000) 49 #define APMIXED_BASE (IO_PHYS + 0x209000) 50 #define TRNG_BASE (IO_PHYS + 0x20F000) 51 #define MT_GIC_BASE (IO_PHYS + 0x220000) 52 #define PLAT_MT_CCI_BASE (IO_PHYS + 0x390000) 53 54 /* Aggregate of all devices in the first GB */ 55 #define MTK_DEV_RNG0_BASE IO_PHYS 56 #define MTK_DEV_RNG0_SIZE 0x400000 57 #define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000) 58 #define MTK_DEV_RNG1_SIZE 0x4000000 59 60 /******************************************************************************* 61 * UART related constants 62 ******************************************************************************/ 63 #define MT8173_UART0_BASE (IO_PHYS + 0x01002000) 64 #define MT8173_UART1_BASE (IO_PHYS + 0x01003000) 65 #define MT8173_UART2_BASE (IO_PHYS + 0x01004000) 66 #define MT8173_UART3_BASE (IO_PHYS + 0x01005000) 67 68 #define MT8173_BAUDRATE (115200) 69 #define MT8173_UART_CLOCK (26000000) 70 71 /******************************************************************************* 72 * System counter frequency related constants 73 ******************************************************************************/ 74 #define SYS_COUNTER_FREQ_IN_TICKS 13000000 75 #define SYS_COUNTER_FREQ_IN_MHZ 13 76 77 /******************************************************************************* 78 * GIC-400 & interrupt handling related constants 79 ******************************************************************************/ 80 81 /* Base MTK_platform compatible GIC memory map */ 82 #define BASE_GICD_BASE (MT_GIC_BASE + 0x1000) 83 #define BASE_GICC_BASE (MT_GIC_BASE + 0x2000) 84 #define BASE_GICR_BASE 0 /* no GICR in GIC-400 */ 85 #define BASE_GICH_BASE (MT_GIC_BASE + 0x4000) 86 #define BASE_GICV_BASE (MT_GIC_BASE + 0x6000) 87 #define INT_POL_CTL0 0x10200620 88 89 #define GIC_PRIVATE_SIGNALS (32) 90 91 /******************************************************************************* 92 * CCI-400 related constants 93 ******************************************************************************/ 94 #define PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX 4 95 #define PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 3 96 97 /******************************************************************************* 98 * WDT related constants 99 ******************************************************************************/ 100 #define MTK_WDT_BASE (RGU_BASE + 0) 101 #define MTK_WDT_SWRST (MTK_WDT_BASE + 0x0014) 102 103 #define MTK_WDT_MODE_DUAL_MODE 0x0040 104 #define MTK_WDT_MODE_IRQ 0x0008 105 #define MTK_WDT_MODE_KEY 0x22000000 106 #define MTK_WDT_MODE_EXTEN 0x0004 107 #define MTK_WDT_SWRST_KEY 0x1209 108 109 /* FIQ platform related define */ 110 #define MT_IRQ_SEC_SGI_0 8 111 #define MT_IRQ_SEC_SGI_1 9 112 #define MT_IRQ_SEC_SGI_2 10 113 #define MT_IRQ_SEC_SGI_3 11 114 #define MT_IRQ_SEC_SGI_4 12 115 #define MT_IRQ_SEC_SGI_5 13 116 #define MT_IRQ_SEC_SGI_6 14 117 #define MT_IRQ_SEC_SGI_7 15 118 119 #endif /* __MT8173_DEF_H__ */ 120