1 /* 2 * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __MT8173_DEF_H__ 32 #define __MT8173_DEF_H__ 33 34 #if RESET_TO_BL31 35 #error "MT8173 is incompatible with RESET_TO_BL31!" 36 #endif 37 38 #define MT8173_PRIMARY_CPU 0x0 39 40 /* Register base address */ 41 #define IO_PHYS (0x10000000) 42 #define INFRACFG_AO_BASE (IO_PHYS + 0x1000) 43 #define SRAMROM_SEC_BASE (IO_PHYS + 0x1800) 44 #define PERI_CON_BASE (IO_PHYS + 0x3000) 45 #define GPIO_BASE (IO_PHYS + 0x5000) 46 #define SPM_BASE (IO_PHYS + 0x6000) 47 #define RGU_BASE (IO_PHYS + 0x7000) 48 #define PMIC_WRAP_BASE (IO_PHYS + 0xD000) 49 #define DEVAPC0_BASE (IO_PHYS + 0xE000) 50 #define MCUCFG_BASE (IO_PHYS + 0x200000) 51 #define APMIXED_BASE (IO_PHYS + 0x209000) 52 #define TRNG_BASE (IO_PHYS + 0x20F000) 53 #define CRYPT_BASE (IO_PHYS + 0x210000) 54 #define MT_GIC_BASE (IO_PHYS + 0x220000) 55 #define PLAT_MT_CCI_BASE (IO_PHYS + 0x390000) 56 57 /* Aggregate of all devices in the first GB */ 58 #define MTK_DEV_RNG0_BASE IO_PHYS 59 #define MTK_DEV_RNG0_SIZE 0x400000 60 #define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000) 61 #define MTK_DEV_RNG1_SIZE 0x4000000 62 63 /* SRAMROM related registers */ 64 #define SRAMROM_SEC_CTRL (SRAMROM_SEC_BASE + 0x4) 65 #define SRAMROM_SEC_ADDR (SRAMROM_SEC_BASE + 0x8) 66 67 /* DEVAPC0 related registers */ 68 #define DEVAPC0_MAS_SEC_0 (DEVAPC0_BASE + 0x500) 69 #define DEVAPC0_APC_CON (DEVAPC0_BASE + 0xF00) 70 71 /******************************************************************************* 72 * UART related constants 73 ******************************************************************************/ 74 #define MT8173_UART0_BASE (IO_PHYS + 0x01002000) 75 #define MT8173_UART1_BASE (IO_PHYS + 0x01003000) 76 #define MT8173_UART2_BASE (IO_PHYS + 0x01004000) 77 #define MT8173_UART3_BASE (IO_PHYS + 0x01005000) 78 79 #define MT8173_BAUDRATE (115200) 80 #define MT8173_UART_CLOCK (26000000) 81 82 /******************************************************************************* 83 * System counter frequency related constants 84 ******************************************************************************/ 85 #define SYS_COUNTER_FREQ_IN_TICKS 13000000 86 87 /******************************************************************************* 88 * GIC-400 & interrupt handling related constants 89 ******************************************************************************/ 90 91 /* Base MTK_platform compatible GIC memory map */ 92 #define BASE_GICD_BASE (MT_GIC_BASE + 0x1000) 93 #define BASE_GICC_BASE (MT_GIC_BASE + 0x2000) 94 #define BASE_GICR_BASE 0 /* no GICR in GIC-400 */ 95 #define BASE_GICH_BASE (MT_GIC_BASE + 0x4000) 96 #define BASE_GICV_BASE (MT_GIC_BASE + 0x6000) 97 #define INT_POL_CTL0 0x10200620 98 99 #define GIC_PRIVATE_SIGNALS (32) 100 101 /******************************************************************************* 102 * CCI-400 related constants 103 ******************************************************************************/ 104 #define PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX 4 105 #define PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 3 106 107 /******************************************************************************* 108 * WDT related constants 109 ******************************************************************************/ 110 #define MTK_WDT_BASE (RGU_BASE + 0) 111 #define MTK_WDT_SWRST (MTK_WDT_BASE + 0x0014) 112 113 #define MTK_WDT_MODE_DUAL_MODE 0x0040 114 #define MTK_WDT_MODE_IRQ 0x0008 115 #define MTK_WDT_MODE_KEY 0x22000000 116 #define MTK_WDT_MODE_EXTEN 0x0004 117 #define MTK_WDT_SWRST_KEY 0x1209 118 119 /* FIQ platform related define */ 120 #define MT_IRQ_SEC_SGI_0 8 121 #define MT_IRQ_SEC_SGI_1 9 122 #define MT_IRQ_SEC_SGI_2 10 123 #define MT_IRQ_SEC_SGI_3 11 124 #define MT_IRQ_SEC_SGI_4 12 125 #define MT_IRQ_SEC_SGI_5 13 126 #define MT_IRQ_SEC_SGI_6 14 127 #define MT_IRQ_SEC_SGI_7 15 128 129 /* 130 * Macros for local power states in MTK platforms encoded by State-ID field 131 * within the power-state parameter. 132 */ 133 /* Local power state for power domains in Run state. */ 134 #define MTK_LOCAL_STATE_RUN 0 135 /* Local power state for retention. Valid only for CPU power domains */ 136 #define MTK_LOCAL_STATE_RET 1 137 /* Local power state for OFF/power-down. Valid for CPU and cluster power 138 * domains 139 */ 140 #define MTK_LOCAL_STATE_OFF 2 141 142 #if PSCI_EXTENDED_STATE_ID 143 /* 144 * Macros used to parse state information from State-ID if it is using the 145 * recommended encoding for State-ID. 146 */ 147 #define MTK_LOCAL_PSTATE_WIDTH 4 148 #define MTK_LOCAL_PSTATE_MASK ((1 << MTK_LOCAL_PSTATE_WIDTH) - 1) 149 150 /* Macros to construct the composite power state */ 151 152 /* Make composite power state parameter till power level 0 */ 153 154 #define mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 155 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) 156 #else 157 #define mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 158 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 159 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ 160 ((type) << PSTATE_TYPE_SHIFT)) 161 162 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 163 164 /* Make composite power state parameter till power level 1 */ 165 #define mtk_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ 166 (((lvl1_state) << MTK_LOCAL_PSTATE_WIDTH) | \ 167 mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) 168 169 /* Make composite power state parameter till power level 2 */ 170 #define mtk_make_pwrstate_lvl2( \ 171 lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ 172 (((lvl2_state) << (MTK_LOCAL_PSTATE_WIDTH * 2)) | \ 173 mtk_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) 174 175 176 #endif /* __MT8173_DEF_H__ */ 177