1*e2a65959SJimmy Huang /* 2*e2a65959SJimmy Huang * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. 3*e2a65959SJimmy Huang * 4*e2a65959SJimmy Huang * Redistribution and use in source and binary forms, with or without 5*e2a65959SJimmy Huang * modification, are permitted provided that the following conditions are met: 6*e2a65959SJimmy Huang * 7*e2a65959SJimmy Huang * Redistributions of source code must retain the above copyright notice, this 8*e2a65959SJimmy Huang * list of conditions and the following disclaimer. 9*e2a65959SJimmy Huang * 10*e2a65959SJimmy Huang * Redistributions in binary form must reproduce the above copyright notice, 11*e2a65959SJimmy Huang * this list of conditions and the following disclaimer in the documentation 12*e2a65959SJimmy Huang * and/or other materials provided with the distribution. 13*e2a65959SJimmy Huang * 14*e2a65959SJimmy Huang * Neither the name of ARM nor the names of its contributors may be used 15*e2a65959SJimmy Huang * to endorse or promote products derived from this software without specific 16*e2a65959SJimmy Huang * prior written permission. 17*e2a65959SJimmy Huang * 18*e2a65959SJimmy Huang * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*e2a65959SJimmy Huang * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*e2a65959SJimmy Huang * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*e2a65959SJimmy Huang * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*e2a65959SJimmy Huang * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*e2a65959SJimmy Huang * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*e2a65959SJimmy Huang * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*e2a65959SJimmy Huang * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*e2a65959SJimmy Huang * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*e2a65959SJimmy Huang * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*e2a65959SJimmy Huang * POSSIBILITY OF SUCH DAMAGE. 29*e2a65959SJimmy Huang */ 30*e2a65959SJimmy Huang 31*e2a65959SJimmy Huang #ifndef __MT8173_DEF_H__ 32*e2a65959SJimmy Huang #define __MT8173_DEF_H__ 33*e2a65959SJimmy Huang 34*e2a65959SJimmy Huang #if RESET_TO_BL31 35*e2a65959SJimmy Huang #error "MT8173 is incompatible with RESET_TO_BL31!" 36*e2a65959SJimmy Huang #endif 37*e2a65959SJimmy Huang 38*e2a65959SJimmy Huang #define MT8173_PRIMARY_CPU 0x0 39*e2a65959SJimmy Huang 40*e2a65959SJimmy Huang /* Register base address */ 41*e2a65959SJimmy Huang #define IO_PHYS (0x10000000) 42*e2a65959SJimmy Huang #define INFRACFG_AO_BASE (IO_PHYS + 0x1000) 43*e2a65959SJimmy Huang #define PERI_CON_BASE (IO_PHYS + 0x3000) 44*e2a65959SJimmy Huang #define GPIO_BASE (IO_PHYS + 0x5000) 45*e2a65959SJimmy Huang #define SPM_BASE (IO_PHYS + 0x6000) 46*e2a65959SJimmy Huang #define RGU_BASE (IO_PHYS + 0x7000) 47*e2a65959SJimmy Huang #define PMIC_WRAP_BASE (IO_PHYS + 0xD000) 48*e2a65959SJimmy Huang #define MCUCFG_BASE (IO_PHYS + 0x200000) 49*e2a65959SJimmy Huang #define TRNG_BASE (IO_PHYS + 0x20F000) 50*e2a65959SJimmy Huang #define MT_GIC_BASE (IO_PHYS + 0x220000) 51*e2a65959SJimmy Huang #define PLAT_MT_CCI_BASE (IO_PHYS + 0x390000) 52*e2a65959SJimmy Huang 53*e2a65959SJimmy Huang /* Aggregate of all devices in the first GB */ 54*e2a65959SJimmy Huang #define MTK_DEV_RNG0_BASE IO_PHYS 55*e2a65959SJimmy Huang #define MTK_DEV_RNG0_SIZE 0x400000 56*e2a65959SJimmy Huang #define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000) 57*e2a65959SJimmy Huang #define MTK_DEV_RNG1_SIZE 0x4000000 58*e2a65959SJimmy Huang 59*e2a65959SJimmy Huang /******************************************************************************* 60*e2a65959SJimmy Huang * UART related constants 61*e2a65959SJimmy Huang ******************************************************************************/ 62*e2a65959SJimmy Huang #define MT8173_UART0_BASE (IO_PHYS + 0x01002000) 63*e2a65959SJimmy Huang #define MT8173_UART1_BASE (IO_PHYS + 0x01003000) 64*e2a65959SJimmy Huang #define MT8173_UART2_BASE (IO_PHYS + 0x01004000) 65*e2a65959SJimmy Huang #define MT8173_UART3_BASE (IO_PHYS + 0x01005000) 66*e2a65959SJimmy Huang 67*e2a65959SJimmy Huang #define MT8173_BAUDRATE (115200) 68*e2a65959SJimmy Huang #define MT8173_UART_CLOCK (26000000) 69*e2a65959SJimmy Huang 70*e2a65959SJimmy Huang /******************************************************************************* 71*e2a65959SJimmy Huang * System counter frequency related constants 72*e2a65959SJimmy Huang ******************************************************************************/ 73*e2a65959SJimmy Huang #define SYS_COUNTER_FREQ_IN_TICKS 13000000 74*e2a65959SJimmy Huang #define SYS_COUNTER_FREQ_IN_MHZ 13 75*e2a65959SJimmy Huang 76*e2a65959SJimmy Huang /******************************************************************************* 77*e2a65959SJimmy Huang * GIC-400 & interrupt handling related constants 78*e2a65959SJimmy Huang ******************************************************************************/ 79*e2a65959SJimmy Huang 80*e2a65959SJimmy Huang /* Base MTK_platform compatible GIC memory map */ 81*e2a65959SJimmy Huang #define BASE_GICD_BASE (MT_GIC_BASE + 0x1000) 82*e2a65959SJimmy Huang #define BASE_GICC_BASE (MT_GIC_BASE + 0x2000) 83*e2a65959SJimmy Huang #define BASE_GICR_BASE 0 /* no GICR in GIC-400 */ 84*e2a65959SJimmy Huang #define BASE_GICH_BASE (MT_GIC_BASE + 0x4000) 85*e2a65959SJimmy Huang #define BASE_GICV_BASE (MT_GIC_BASE + 0x6000) 86*e2a65959SJimmy Huang #define INT_POL_CTL0 0x10200620 87*e2a65959SJimmy Huang 88*e2a65959SJimmy Huang #define GIC_PRIVATE_SIGNALS (32) 89*e2a65959SJimmy Huang 90*e2a65959SJimmy Huang /******************************************************************************* 91*e2a65959SJimmy Huang * CCI-400 related constants 92*e2a65959SJimmy Huang ******************************************************************************/ 93*e2a65959SJimmy Huang #define PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX 4 94*e2a65959SJimmy Huang #define PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 3 95*e2a65959SJimmy Huang 96*e2a65959SJimmy Huang /******************************************************************************* 97*e2a65959SJimmy Huang * WDT related constants 98*e2a65959SJimmy Huang ******************************************************************************/ 99*e2a65959SJimmy Huang #define MTK_WDT_BASE (RGU_BASE + 0) 100*e2a65959SJimmy Huang #define MTK_WDT_SWRST (MTK_WDT_BASE + 0x0014) 101*e2a65959SJimmy Huang 102*e2a65959SJimmy Huang #define MTK_WDT_MODE_DUAL_MODE 0x0040 103*e2a65959SJimmy Huang #define MTK_WDT_MODE_IRQ 0x0008 104*e2a65959SJimmy Huang #define MTK_WDT_MODE_KEY 0x22000000 105*e2a65959SJimmy Huang #define MTK_WDT_MODE_EXTEN 0x0004 106*e2a65959SJimmy Huang #define MTK_WDT_SWRST_KEY 0x1209 107*e2a65959SJimmy Huang 108*e2a65959SJimmy Huang /* FIQ platform related define */ 109*e2a65959SJimmy Huang #define MT_IRQ_SEC_SGI_0 8 110*e2a65959SJimmy Huang #define MT_IRQ_SEC_SGI_1 9 111*e2a65959SJimmy Huang #define MT_IRQ_SEC_SGI_2 10 112*e2a65959SJimmy Huang #define MT_IRQ_SEC_SGI_3 11 113*e2a65959SJimmy Huang #define MT_IRQ_SEC_SGI_4 12 114*e2a65959SJimmy Huang #define MT_IRQ_SEC_SGI_5 13 115*e2a65959SJimmy Huang #define MT_IRQ_SEC_SGI_6 14 116*e2a65959SJimmy Huang #define MT_IRQ_SEC_SGI_7 15 117*e2a65959SJimmy Huang 118*e2a65959SJimmy Huang #endif /* __MT8173_DEF_H__ */ 119