1e2a65959SJimmy Huang /* 2e2a65959SJimmy Huang * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. 3e2a65959SJimmy Huang * 4e2a65959SJimmy Huang * Redistribution and use in source and binary forms, with or without 5e2a65959SJimmy Huang * modification, are permitted provided that the following conditions are met: 6e2a65959SJimmy Huang * 7e2a65959SJimmy Huang * Redistributions of source code must retain the above copyright notice, this 8e2a65959SJimmy Huang * list of conditions and the following disclaimer. 9e2a65959SJimmy Huang * 10e2a65959SJimmy Huang * Redistributions in binary form must reproduce the above copyright notice, 11e2a65959SJimmy Huang * this list of conditions and the following disclaimer in the documentation 12e2a65959SJimmy Huang * and/or other materials provided with the distribution. 13e2a65959SJimmy Huang * 14e2a65959SJimmy Huang * Neither the name of ARM nor the names of its contributors may be used 15e2a65959SJimmy Huang * to endorse or promote products derived from this software without specific 16e2a65959SJimmy Huang * prior written permission. 17e2a65959SJimmy Huang * 18e2a65959SJimmy Huang * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19e2a65959SJimmy Huang * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20e2a65959SJimmy Huang * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21e2a65959SJimmy Huang * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22e2a65959SJimmy Huang * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23e2a65959SJimmy Huang * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24e2a65959SJimmy Huang * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25e2a65959SJimmy Huang * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26e2a65959SJimmy Huang * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27e2a65959SJimmy Huang * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28e2a65959SJimmy Huang * POSSIBILITY OF SUCH DAMAGE. 29e2a65959SJimmy Huang */ 30e2a65959SJimmy Huang 31e2a65959SJimmy Huang #ifndef __MT8173_DEF_H__ 32e2a65959SJimmy Huang #define __MT8173_DEF_H__ 33e2a65959SJimmy Huang 34e2a65959SJimmy Huang #if RESET_TO_BL31 35e2a65959SJimmy Huang #error "MT8173 is incompatible with RESET_TO_BL31!" 36e2a65959SJimmy Huang #endif 37e2a65959SJimmy Huang 38e2a65959SJimmy Huang #define MT8173_PRIMARY_CPU 0x0 39e2a65959SJimmy Huang 40e2a65959SJimmy Huang /* Register base address */ 41e2a65959SJimmy Huang #define IO_PHYS (0x10000000) 42e2a65959SJimmy Huang #define INFRACFG_AO_BASE (IO_PHYS + 0x1000) 43a1e0c01fSJimmy Huang #define SRAMROM_SEC_BASE (IO_PHYS + 0x1800) 44e2a65959SJimmy Huang #define PERI_CON_BASE (IO_PHYS + 0x3000) 45e2a65959SJimmy Huang #define GPIO_BASE (IO_PHYS + 0x5000) 46e2a65959SJimmy Huang #define SPM_BASE (IO_PHYS + 0x6000) 47e2a65959SJimmy Huang #define RGU_BASE (IO_PHYS + 0x7000) 48e2a65959SJimmy Huang #define PMIC_WRAP_BASE (IO_PHYS + 0xD000) 49a1e0c01fSJimmy Huang #define DEVAPC0_BASE (IO_PHYS + 0xE000) 50e2a65959SJimmy Huang #define MCUCFG_BASE (IO_PHYS + 0x200000) 51b99d961cSJimmy Huang #define APMIXED_BASE (IO_PHYS + 0x209000) 52e2a65959SJimmy Huang #define TRNG_BASE (IO_PHYS + 0x20F000) 53*7ace1cc0SYi Zheng #define CRYPT_BASE (IO_PHYS + 0x210000) 54e2a65959SJimmy Huang #define MT_GIC_BASE (IO_PHYS + 0x220000) 55e2a65959SJimmy Huang #define PLAT_MT_CCI_BASE (IO_PHYS + 0x390000) 56e2a65959SJimmy Huang 57e2a65959SJimmy Huang /* Aggregate of all devices in the first GB */ 58e2a65959SJimmy Huang #define MTK_DEV_RNG0_BASE IO_PHYS 59e2a65959SJimmy Huang #define MTK_DEV_RNG0_SIZE 0x400000 60e2a65959SJimmy Huang #define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000) 61e2a65959SJimmy Huang #define MTK_DEV_RNG1_SIZE 0x4000000 62e2a65959SJimmy Huang 63a1e0c01fSJimmy Huang /* SRAMROM related registers */ 64a1e0c01fSJimmy Huang #define SRAMROM_SEC_CTRL (SRAMROM_SEC_BASE + 0x4) 65a1e0c01fSJimmy Huang #define SRAMROM_SEC_ADDR (SRAMROM_SEC_BASE + 0x8) 66a1e0c01fSJimmy Huang 67a1e0c01fSJimmy Huang /* DEVAPC0 related registers */ 68a1e0c01fSJimmy Huang #define DEVAPC0_MAS_SEC_0 (DEVAPC0_BASE + 0x500) 69a1e0c01fSJimmy Huang #define DEVAPC0_APC_CON (DEVAPC0_BASE + 0xF00) 70a1e0c01fSJimmy Huang 71e2a65959SJimmy Huang /******************************************************************************* 72e2a65959SJimmy Huang * UART related constants 73e2a65959SJimmy Huang ******************************************************************************/ 74e2a65959SJimmy Huang #define MT8173_UART0_BASE (IO_PHYS + 0x01002000) 75e2a65959SJimmy Huang #define MT8173_UART1_BASE (IO_PHYS + 0x01003000) 76e2a65959SJimmy Huang #define MT8173_UART2_BASE (IO_PHYS + 0x01004000) 77e2a65959SJimmy Huang #define MT8173_UART3_BASE (IO_PHYS + 0x01005000) 78e2a65959SJimmy Huang 79e2a65959SJimmy Huang #define MT8173_BAUDRATE (115200) 80e2a65959SJimmy Huang #define MT8173_UART_CLOCK (26000000) 81e2a65959SJimmy Huang 82e2a65959SJimmy Huang /******************************************************************************* 83e2a65959SJimmy Huang * System counter frequency related constants 84e2a65959SJimmy Huang ******************************************************************************/ 85e2a65959SJimmy Huang #define SYS_COUNTER_FREQ_IN_TICKS 13000000 86e2a65959SJimmy Huang #define SYS_COUNTER_FREQ_IN_MHZ 13 87e2a65959SJimmy Huang 88e2a65959SJimmy Huang /******************************************************************************* 89e2a65959SJimmy Huang * GIC-400 & interrupt handling related constants 90e2a65959SJimmy Huang ******************************************************************************/ 91e2a65959SJimmy Huang 92e2a65959SJimmy Huang /* Base MTK_platform compatible GIC memory map */ 93e2a65959SJimmy Huang #define BASE_GICD_BASE (MT_GIC_BASE + 0x1000) 94e2a65959SJimmy Huang #define BASE_GICC_BASE (MT_GIC_BASE + 0x2000) 95e2a65959SJimmy Huang #define BASE_GICR_BASE 0 /* no GICR in GIC-400 */ 96e2a65959SJimmy Huang #define BASE_GICH_BASE (MT_GIC_BASE + 0x4000) 97e2a65959SJimmy Huang #define BASE_GICV_BASE (MT_GIC_BASE + 0x6000) 98e2a65959SJimmy Huang #define INT_POL_CTL0 0x10200620 99e2a65959SJimmy Huang 100e2a65959SJimmy Huang #define GIC_PRIVATE_SIGNALS (32) 101e2a65959SJimmy Huang 102e2a65959SJimmy Huang /******************************************************************************* 103e2a65959SJimmy Huang * CCI-400 related constants 104e2a65959SJimmy Huang ******************************************************************************/ 105e2a65959SJimmy Huang #define PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX 4 106e2a65959SJimmy Huang #define PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 3 107e2a65959SJimmy Huang 108e2a65959SJimmy Huang /******************************************************************************* 109e2a65959SJimmy Huang * WDT related constants 110e2a65959SJimmy Huang ******************************************************************************/ 111e2a65959SJimmy Huang #define MTK_WDT_BASE (RGU_BASE + 0) 112e2a65959SJimmy Huang #define MTK_WDT_SWRST (MTK_WDT_BASE + 0x0014) 113e2a65959SJimmy Huang 114e2a65959SJimmy Huang #define MTK_WDT_MODE_DUAL_MODE 0x0040 115e2a65959SJimmy Huang #define MTK_WDT_MODE_IRQ 0x0008 116e2a65959SJimmy Huang #define MTK_WDT_MODE_KEY 0x22000000 117e2a65959SJimmy Huang #define MTK_WDT_MODE_EXTEN 0x0004 118e2a65959SJimmy Huang #define MTK_WDT_SWRST_KEY 0x1209 119e2a65959SJimmy Huang 120e2a65959SJimmy Huang /* FIQ platform related define */ 121e2a65959SJimmy Huang #define MT_IRQ_SEC_SGI_0 8 122e2a65959SJimmy Huang #define MT_IRQ_SEC_SGI_1 9 123e2a65959SJimmy Huang #define MT_IRQ_SEC_SGI_2 10 124e2a65959SJimmy Huang #define MT_IRQ_SEC_SGI_3 11 125e2a65959SJimmy Huang #define MT_IRQ_SEC_SGI_4 12 126e2a65959SJimmy Huang #define MT_IRQ_SEC_SGI_5 13 127e2a65959SJimmy Huang #define MT_IRQ_SEC_SGI_6 14 128e2a65959SJimmy Huang #define MT_IRQ_SEC_SGI_7 15 129e2a65959SJimmy Huang 130e2a65959SJimmy Huang #endif /* __MT8173_DEF_H__ */ 131