xref: /rk3399_ARM-atf/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c (revision 7d116dccab2249a692181ba9521a52277e86591c)
1*7d116dccSCC Ma /*
2*7d116dccSCC Ma  * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3*7d116dccSCC Ma  *
4*7d116dccSCC Ma  * Redistribution and use in source and binary forms, with or without
5*7d116dccSCC Ma  * modification, are permitted provided that the following conditions are met:
6*7d116dccSCC Ma  *
7*7d116dccSCC Ma  * Redistributions of source code must retain the above copyright notice, this
8*7d116dccSCC Ma  * list of conditions and the following disclaimer.
9*7d116dccSCC Ma  *
10*7d116dccSCC Ma  * Redistributions in binary form must reproduce the above copyright notice,
11*7d116dccSCC Ma  * this list of conditions and the following disclaimer in the documentation
12*7d116dccSCC Ma  * and/or other materials provided with the distribution.
13*7d116dccSCC Ma  *
14*7d116dccSCC Ma  * Neither the name of ARM nor the names of its contributors may be used
15*7d116dccSCC Ma  * to endorse or promote products derived from this software without specific
16*7d116dccSCC Ma  * prior written permission.
17*7d116dccSCC Ma  *
18*7d116dccSCC Ma  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19*7d116dccSCC Ma  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20*7d116dccSCC Ma  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21*7d116dccSCC Ma  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22*7d116dccSCC Ma  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23*7d116dccSCC Ma  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24*7d116dccSCC Ma  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25*7d116dccSCC Ma  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26*7d116dccSCC Ma  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27*7d116dccSCC Ma  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28*7d116dccSCC Ma  * POSSIBILITY OF SUCH DAMAGE.
29*7d116dccSCC Ma  */
30*7d116dccSCC Ma #include <arch.h>
31*7d116dccSCC Ma #include <debug.h>
32*7d116dccSCC Ma #include <mmio.h>
33*7d116dccSCC Ma #include <mt8173_def.h>
34*7d116dccSCC Ma #include <platform.h>
35*7d116dccSCC Ma #include <platform_def.h>
36*7d116dccSCC Ma #include <spm.h>
37*7d116dccSCC Ma #include <spm_hotplug.h>
38*7d116dccSCC Ma #include <spm_mcdi.h>
39*7d116dccSCC Ma 
40*7d116dccSCC Ma /*
41*7d116dccSCC Ma  * System Power Manager (SPM) is a hardware module, which controls cpu or
42*7d116dccSCC Ma  * system power for different power scenarios using different firmware.
43*7d116dccSCC Ma  * This driver controls the cpu power in cpu idle power saving state.
44*7d116dccSCC Ma  */
45*7d116dccSCC Ma 
46*7d116dccSCC Ma #define WAKE_SRC_FOR_MCDI	(WAKE_SRC_SYSPWREQ | WAKE_SRC_CPU_IRQ)
47*7d116dccSCC Ma #define PCM_MCDI_HANDSHAKE_SYNC	0xbeefbeef
48*7d116dccSCC Ma #define PCM_MCDI_HANDSHAKE_ACK	0xdeaddead
49*7d116dccSCC Ma #define PCM_MCDI_UPDATE_INFORM	0xabcdabcd
50*7d116dccSCC Ma #define PCM_MCDI_CKECK_DONE	0x12345678
51*7d116dccSCC Ma #define PCM_MCDI_ALL_CORE_AWAKE	0x0
52*7d116dccSCC Ma #define PCM_MCDI_OFFLOADED	0xaa55aa55
53*7d116dccSCC Ma 
54*7d116dccSCC Ma static const unsigned int mcdi_binary[] = {
55*7d116dccSCC Ma 	0x1212841f, 0xe2e00036, 0xe2e0003e, 0x1380201f, 0xe2e0003c, 0xe2a00000,
56*7d116dccSCC Ma 	0x1b80001f, 0x20000080, 0xe2e0007c, 0x1b80001f, 0x20000003, 0xe2e0005c,
57*7d116dccSCC Ma 	0xe2e0004c, 0xe2e0004d, 0xf0000000, 0x17c07c1f, 0xe2e0004f, 0xe2e0006f,
58*7d116dccSCC Ma 	0xe2e0002f, 0xe2a00001, 0x1b80001f, 0x20000080, 0xe2e0002e, 0xe2e0003e,
59*7d116dccSCC Ma 	0xe2e00032, 0xf0000000, 0x17c07c1f, 0x1212841f, 0xe2e00026, 0xe2e0002e,
60*7d116dccSCC Ma 	0x1380201f, 0x1a00001f, 0x100062b4, 0x1910001f, 0x100062b4, 0x81322804,
61*7d116dccSCC Ma 	0xe2000004, 0x81202804, 0xe2000004, 0x1b80001f, 0x20000034, 0x1910001f,
62*7d116dccSCC Ma 	0x100062b4, 0x81142804, 0xd8000524, 0x17c07c1f, 0xe2e0000e, 0xe2e0000c,
63*7d116dccSCC Ma 	0xe2e0000d, 0xf0000000, 0x17c07c1f, 0xe2e0002d, 0x1a00001f, 0x100062b4,
64*7d116dccSCC Ma 	0x1910001f, 0x100062b4, 0xa1002804, 0xe2000004, 0xa1122804, 0xe2000004,
65*7d116dccSCC Ma 	0x1b80001f, 0x20000080, 0x1910001f, 0x100062b4, 0x81142804, 0xd82007c4,
66*7d116dccSCC Ma 	0x17c07c1f, 0xe2e0002f, 0xe2e0002b, 0xe2e00023, 0x1380201f, 0xe2e00022,
67*7d116dccSCC Ma 	0xf0000000, 0x17c07c1f, 0x18c0001f, 0x10006b6c, 0x1910001f, 0x10006b6c,
68*7d116dccSCC Ma 	0xa1002804, 0xe0c00004, 0xf0000000, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
69*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
70*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
71*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
72*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
73*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
74*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
75*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
76*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
77*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
78*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
79*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
80*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
81*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
82*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
83*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
84*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
85*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
86*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
87*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
88*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
89*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
90*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
91*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
92*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
93*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
94*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
95*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
96*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
97*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
98*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
99*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
100*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
101*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
102*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
103*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
104*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
105*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
106*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
107*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
108*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
109*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
110*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
111*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
112*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
113*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
114*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
115*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
116*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
117*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
118*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
119*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
120*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
121*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
122*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
123*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
124*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
125*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
126*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
127*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
128*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
129*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
130*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
131*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
132*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
133*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
134*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
135*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
136*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
137*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
138*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
139*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
140*7d116dccSCC Ma 	0x17c07c1f, 0x17c07c1f, 0x1840001f, 0x00000001, 0x11407c1f, 0xe8208000,
141*7d116dccSCC Ma 	0x10006b6c, 0xa0000000, 0xe8208000, 0x10006310, 0x0b160008, 0x1900001f,
142*7d116dccSCC Ma 	0x000f7bde, 0x1a00001f, 0x10200268, 0xe2000004, 0xe8208000, 0x10006600,
143*7d116dccSCC Ma 	0x00000000, 0xc2800940, 0x1280041f, 0x1b00001f, 0x21000001, 0x1b80001f,
144*7d116dccSCC Ma 	0xd0010000, 0xc2800940, 0x1290841f, 0x69200006, 0xbeefbeef, 0xd8204764,
145*7d116dccSCC Ma 	0x17c07c1f, 0xc2800940, 0x1291041f, 0x1910001f, 0x10006358, 0x810b1001,
146*7d116dccSCC Ma 	0xd80043e4, 0x17c07c1f, 0x1980001f, 0xdeaddead, 0x69200006, 0xabcdabcd,
147*7d116dccSCC Ma 	0xd82044c4, 0x17c07c1f, 0xc2800940, 0x1291841f, 0x88900001, 0x10006814,
148*7d116dccSCC Ma 	0x1910001f, 0x10006400, 0x81271002, 0x1880001f, 0x10006600, 0xe0800004,
149*7d116dccSCC Ma 	0x1910001f, 0x10006358, 0x810b1001, 0xd8004684, 0x17c07c1f, 0x1980001f,
150*7d116dccSCC Ma 	0x12345678, 0x60a07c05, 0x89100002, 0x10006600, 0x80801001, 0xd8007142,
151*7d116dccSCC Ma 	0x17c07c1f, 0xc2800940, 0x1292041f, 0x1a10001f, 0x10006720, 0x82002001,
152*7d116dccSCC Ma 	0x82201408, 0xd8204a08, 0x17c07c1f, 0x1a40001f, 0x10006200, 0x1a80001f,
153*7d116dccSCC Ma 	0x1000625c, 0xc2400200, 0x17c07c1f, 0xa1400405, 0xc2800940, 0x1292841f,
154*7d116dccSCC Ma 	0x1a10001f, 0x10006720, 0x8200a001, 0x82209408, 0xd8204be8, 0x17c07c1f,
155*7d116dccSCC Ma 	0x1a40001f, 0x10006218, 0x1a80001f, 0x10006264, 0xc2400200, 0x17c07c1f,
156*7d116dccSCC Ma 	0xa1508405, 0xc2800940, 0x1293041f, 0x1a10001f, 0x10006720, 0x82012001,
157*7d116dccSCC Ma 	0x82211408, 0xd8204dc8, 0x17c07c1f, 0x1a40001f, 0x1000621c, 0x1a80001f,
158*7d116dccSCC Ma 	0x1000626c, 0xc2400200, 0x17c07c1f, 0xa1510405, 0x1a10001f, 0x10006720,
159*7d116dccSCC Ma 	0x8201a001, 0x82219408, 0xd8204f68, 0x17c07c1f, 0x1a40001f, 0x10006220,
160*7d116dccSCC Ma 	0x1a80001f, 0x10006274, 0xc2400200, 0x17c07c1f, 0xa1518405, 0x1a10001f,
161*7d116dccSCC Ma 	0x10006720, 0x82022001, 0x82221408, 0xd82050e8, 0x17c07c1f, 0x1a40001f,
162*7d116dccSCC Ma 	0x100062a0, 0x1280041f, 0xc2400660, 0x17c07c1f, 0xa1520405, 0x1a10001f,
163*7d116dccSCC Ma 	0x10006720, 0x8202a001, 0x82229408, 0xd8205268, 0x17c07c1f, 0x1a40001f,
164*7d116dccSCC Ma 	0x100062a4, 0x1290841f, 0xc2400660, 0x17c07c1f, 0xa1528405, 0x1a10001f,
165*7d116dccSCC Ma 	0x10006720, 0x82032001, 0x82231408, 0xd82053e8, 0x17c07c1f, 0x1a40001f,
166*7d116dccSCC Ma 	0x100062a8, 0x1291041f, 0xc2400660, 0x17c07c1f, 0xa1530405, 0x1a10001f,
167*7d116dccSCC Ma 	0x10006720, 0x8203a001, 0x82239408, 0xd8205568, 0x17c07c1f, 0x1a40001f,
168*7d116dccSCC Ma 	0x100062ac, 0x1291841f, 0xc2400660, 0x17c07c1f, 0xa1538405, 0x1b80001f,
169*7d116dccSCC Ma 	0x20000208, 0xd82070cc, 0x17c07c1f, 0x81001401, 0xd8205964, 0x17c07c1f,
170*7d116dccSCC Ma 	0x1a10001f, 0x10006918, 0x81002001, 0xb1042081, 0xb1003081, 0xb10c3081,
171*7d116dccSCC Ma 	0xd8205964, 0x17c07c1f, 0x1a40001f, 0x10006200, 0x1a80001f, 0x1000625c,
172*7d116dccSCC Ma 	0xc2400000, 0x17c07c1f, 0x89400005, 0xfffffffe, 0xe8208000, 0x10006f00,
173*7d116dccSCC Ma 	0x00000000, 0xe8208000, 0x10006b30, 0x00000000, 0xe8208000, 0x100063e0,
174*7d116dccSCC Ma 	0x00000001, 0x81009401, 0xd8205cc4, 0x17c07c1f, 0x1a10001f, 0x10006918,
175*7d116dccSCC Ma 	0x8100a001, 0xb104a081, 0xb1003081, 0xd8205cc4, 0x17c07c1f, 0x1a40001f,
176*7d116dccSCC Ma 	0x10006218, 0x1a80001f, 0x10006264, 0xc2400000, 0x17c07c1f, 0x89400005,
177*7d116dccSCC Ma 	0xfffffffd, 0xe8208000, 0x10006f04, 0x00000000, 0xe8208000, 0x10006b34,
178*7d116dccSCC Ma 	0x00000000, 0xe8208000, 0x100063e0, 0x00000002, 0x81011401, 0xd8206024,
179*7d116dccSCC Ma 	0x17c07c1f, 0x1a10001f, 0x10006918, 0x81012001, 0xb1052081, 0xb1003081,
180*7d116dccSCC Ma 	0xd8206024, 0x17c07c1f, 0x1a40001f, 0x1000621c, 0x1a80001f, 0x1000626c,
181*7d116dccSCC Ma 	0xc2400000, 0x17c07c1f, 0x89400005, 0xfffffffb, 0xe8208000, 0x10006f08,
182*7d116dccSCC Ma 	0x00000000, 0xe8208000, 0x10006b38, 0x00000000, 0xe8208000, 0x100063e0,
183*7d116dccSCC Ma 	0x00000004, 0x81019401, 0xd8206384, 0x17c07c1f, 0x1a10001f, 0x10006918,
184*7d116dccSCC Ma 	0x8101a001, 0xb105a081, 0xb1003081, 0xd8206384, 0x17c07c1f, 0x1a40001f,
185*7d116dccSCC Ma 	0x10006220, 0x1a80001f, 0x10006274, 0xc2400000, 0x17c07c1f, 0x89400005,
186*7d116dccSCC Ma 	0xfffffff7, 0xe8208000, 0x10006f0c, 0x00000000, 0xe8208000, 0x10006b3c,
187*7d116dccSCC Ma 	0x00000000, 0xe8208000, 0x100063e0, 0x00000008, 0x81021401, 0xd82066c4,
188*7d116dccSCC Ma 	0x17c07c1f, 0x1a10001f, 0x10006918, 0x81022001, 0xb1062081, 0xb1003081,
189*7d116dccSCC Ma 	0xd82066c4, 0x17c07c1f, 0x1a40001f, 0x100062a0, 0x1280041f, 0xc2400360,
190*7d116dccSCC Ma 	0x17c07c1f, 0x89400005, 0xffffffef, 0xe8208000, 0x10006f10, 0x00000000,
191*7d116dccSCC Ma 	0xe8208000, 0x10006b40, 0x00000000, 0xe8208000, 0x100063e0, 0x00000010,
192*7d116dccSCC Ma 	0x81029401, 0xd8206a04, 0x17c07c1f, 0x1a10001f, 0x10006918, 0x8102a001,
193*7d116dccSCC Ma 	0xb106a081, 0xb1003081, 0xd8206a04, 0x17c07c1f, 0x1a40001f, 0x100062a4,
194*7d116dccSCC Ma 	0x1290841f, 0xc2400360, 0x17c07c1f, 0x89400005, 0xffffffdf, 0xe8208000,
195*7d116dccSCC Ma 	0x10006f14, 0x00000000, 0xe8208000, 0x10006b44, 0x00000000, 0xe8208000,
196*7d116dccSCC Ma 	0x100063e0, 0x00000020, 0x81031401, 0xd8206d44, 0x17c07c1f, 0x1a10001f,
197*7d116dccSCC Ma 	0x10006918, 0x81032001, 0xb1072081, 0xb1003081, 0xd8206d44, 0x17c07c1f,
198*7d116dccSCC Ma 	0x1a40001f, 0x100062a8, 0x1291041f, 0xc2400360, 0x17c07c1f, 0x89400005,
199*7d116dccSCC Ma 	0xffffffbf, 0xe8208000, 0x10006f18, 0x00000000, 0xe8208000, 0x10006b48,
200*7d116dccSCC Ma 	0x00000000, 0xe8208000, 0x100063e0, 0x00000040, 0x81039401, 0xd8207084,
201*7d116dccSCC Ma 	0x17c07c1f, 0x1a10001f, 0x10006918, 0x8103a001, 0xb107a081, 0xb1003081,
202*7d116dccSCC Ma 	0xd8207084, 0x17c07c1f, 0x1a40001f, 0x100062ac, 0x1291841f, 0xc2400360,
203*7d116dccSCC Ma 	0x17c07c1f, 0x89400005, 0xffffff7f, 0xe8208000, 0x10006f1c, 0x00000000,
204*7d116dccSCC Ma 	0xe8208000, 0x10006b4c, 0x00000000, 0xe8208000, 0x100063e0, 0x00000080,
205*7d116dccSCC Ma 	0xc2800940, 0x1293841f, 0xd0004260, 0x17c07c1f, 0xc2800940, 0x1294041f,
206*7d116dccSCC Ma 	0xe8208000, 0x10006600, 0x00000000, 0x1ac0001f, 0x55aa55aa, 0x1940001f,
207*7d116dccSCC Ma 	0xaa55aa55, 0xc2800940, 0x1294841f, 0x1b80001f, 0x00001000, 0xf0000000,
208*7d116dccSCC Ma 	0x17c07c1f
209*7d116dccSCC Ma };
210*7d116dccSCC Ma 
211*7d116dccSCC Ma static const struct pcm_desc mcdi_pcm = {
212*7d116dccSCC Ma 	.version = "pcm_mcdi_v0.5_20140721_mt8173_v03.04_20150507",
213*7d116dccSCC Ma 	.base = mcdi_binary,
214*7d116dccSCC Ma 	.size = 919,
215*7d116dccSCC Ma 	.sess = 2,
216*7d116dccSCC Ma 	.replace = 0,
217*7d116dccSCC Ma };
218*7d116dccSCC Ma 
219*7d116dccSCC Ma static struct pwr_ctrl mcdi_ctrl = {
220*7d116dccSCC Ma 	.wake_src = WAKE_SRC_FOR_MCDI,
221*7d116dccSCC Ma 	.wake_src_md32 = 0,
222*7d116dccSCC Ma 	.wfi_op = WFI_OP_OR,
223*7d116dccSCC Ma 	.mcusys_idle_mask = 1,
224*7d116dccSCC Ma 	.ca7top_idle_mask = 1,
225*7d116dccSCC Ma 	.ca15top_idle_mask = 1,
226*7d116dccSCC Ma 	.disp_req_mask = 1,
227*7d116dccSCC Ma 	.mfg_req_mask = 1,
228*7d116dccSCC Ma 	.md32_req_mask = 1,
229*7d116dccSCC Ma };
230*7d116dccSCC Ma 
231*7d116dccSCC Ma static const struct spm_lp_scen spm_mcdi = {
232*7d116dccSCC Ma 	.pcmdesc = &mcdi_pcm,
233*7d116dccSCC Ma 	.pwrctrl = &mcdi_ctrl,
234*7d116dccSCC Ma };
235*7d116dccSCC Ma 
236*7d116dccSCC Ma void spm_mcdi_cpu_wake_up_event(int wake_up_event, int disable_dormant_power)
237*7d116dccSCC Ma {
238*7d116dccSCC Ma 	if (((mmio_read_32(SPM_SLEEP_CPU_WAKEUP_EVENT) & 0x1) == 1)
239*7d116dccSCC Ma 	    && ((mmio_read_32(SPM_CLK_CON) & CC_DISABLE_DORM_PWR) == 0)) {
240*7d116dccSCC Ma 		/* MCDI is offload? */
241*7d116dccSCC Ma 		INFO("%s: SPM_SLEEP_CPU_WAKEUP_EVENT:%x, SPM_CLK_CON %x",
242*7d116dccSCC Ma 		     __func__, mmio_read_32(SPM_SLEEP_CPU_WAKEUP_EVENT),
243*7d116dccSCC Ma 		     mmio_read_32(SPM_CLK_CON));
244*7d116dccSCC Ma 		return;
245*7d116dccSCC Ma 	}
246*7d116dccSCC Ma 	/* Inform SPM that CPU wants to program CPU_WAKEUP_EVENT and
247*7d116dccSCC Ma 	 * DISABLE_CPU_DROM */
248*7d116dccSCC Ma 	mmio_write_32(SPM_PCM_REG_DATA_INI, PCM_MCDI_HANDSHAKE_SYNC);
249*7d116dccSCC Ma 	mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6);
250*7d116dccSCC Ma 	mmio_write_32(SPM_PCM_PWR_IO_EN, 0);
251*7d116dccSCC Ma 
252*7d116dccSCC Ma 	/* Wait SPM's response, can't use sleep api */
253*7d116dccSCC Ma 	while (mmio_read_32(SPM_PCM_REG6_DATA) != PCM_MCDI_HANDSHAKE_ACK)
254*7d116dccSCC Ma 		;
255*7d116dccSCC Ma 
256*7d116dccSCC Ma 	if (disable_dormant_power) {
257*7d116dccSCC Ma 		mmio_setbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR);
258*7d116dccSCC Ma 		while (mmio_read_32(SPM_CLK_CON) !=
259*7d116dccSCC Ma 			(mmio_read_32(SPM_CLK_CON) | CC_DISABLE_DORM_PWR))
260*7d116dccSCC Ma 			;
261*7d116dccSCC Ma 
262*7d116dccSCC Ma 	} else {
263*7d116dccSCC Ma 		mmio_clrbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR);
264*7d116dccSCC Ma 		while (mmio_read_32(SPM_CLK_CON) !=
265*7d116dccSCC Ma 			(mmio_read_32(SPM_CLK_CON) & ~CC_DISABLE_DORM_PWR))
266*7d116dccSCC Ma 			;
267*7d116dccSCC Ma 	}
268*7d116dccSCC Ma 
269*7d116dccSCC Ma 	mmio_write_32(SPM_SLEEP_CPU_WAKEUP_EVENT, wake_up_event);
270*7d116dccSCC Ma 
271*7d116dccSCC Ma 	while (mmio_read_32(SPM_SLEEP_CPU_WAKEUP_EVENT) != wake_up_event)
272*7d116dccSCC Ma 		;
273*7d116dccSCC Ma 
274*7d116dccSCC Ma 	/* Inform SPM to see updated setting */
275*7d116dccSCC Ma 	mmio_write_32(SPM_PCM_REG_DATA_INI, PCM_MCDI_UPDATE_INFORM);
276*7d116dccSCC Ma 	mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6);
277*7d116dccSCC Ma 	mmio_write_32(SPM_PCM_PWR_IO_EN, 0);
278*7d116dccSCC Ma 
279*7d116dccSCC Ma 	while (mmio_read_32(SPM_PCM_REG6_DATA) != PCM_MCDI_CKECK_DONE)
280*7d116dccSCC Ma 		;
281*7d116dccSCC Ma 	/* END OF sequence */
282*7d116dccSCC Ma 
283*7d116dccSCC Ma 	mmio_write_32(SPM_PCM_REG_DATA_INI, 0x0);
284*7d116dccSCC Ma 	mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6);
285*7d116dccSCC Ma 	mmio_write_32(SPM_PCM_PWR_IO_EN, 0);
286*7d116dccSCC Ma }
287*7d116dccSCC Ma 
288*7d116dccSCC Ma void spm_mcdi_wakeup_all_cores(void)
289*7d116dccSCC Ma {
290*7d116dccSCC Ma 	if (is_mcdi_ready() == 0)
291*7d116dccSCC Ma 		return;
292*7d116dccSCC Ma 
293*7d116dccSCC Ma 	spm_mcdi_cpu_wake_up_event(1, 1);
294*7d116dccSCC Ma 	while (mmio_read_32(SPM_PCM_REG5_DATA) != PCM_MCDI_ALL_CORE_AWAKE)
295*7d116dccSCC Ma 		;
296*7d116dccSCC Ma 	spm_mcdi_cpu_wake_up_event(1, 0);
297*7d116dccSCC Ma 	while (mmio_read_32(SPM_PCM_REG5_DATA) != PCM_MCDI_OFFLOADED)
298*7d116dccSCC Ma 		;
299*7d116dccSCC Ma 
300*7d116dccSCC Ma 	spm_clean_after_wakeup();
301*7d116dccSCC Ma 	clear_all_ready();
302*7d116dccSCC Ma }
303*7d116dccSCC Ma 
304*7d116dccSCC Ma void spm_mcdi_wfi_sel_enter(unsigned long mpidr)
305*7d116dccSCC Ma {
306*7d116dccSCC Ma 	int core_id_val = mpidr & MPIDR_CPU_MASK;
307*7d116dccSCC Ma 	int cluster_id = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS;
308*7d116dccSCC Ma 
309*7d116dccSCC Ma 	/* SPM WFI Select by core number */
310*7d116dccSCC Ma 	if (cluster_id) {
311*7d116dccSCC Ma 		switch (core_id_val) {
312*7d116dccSCC Ma 		case 0:
313*7d116dccSCC Ma 			mmio_write_32(SPM_CA15_CPU0_IRQ_MASK, 1);
314*7d116dccSCC Ma 			mmio_write_32(SPM_SLEEP_CA15_WFI0_EN, 1);
315*7d116dccSCC Ma 			break;
316*7d116dccSCC Ma 		case 1:
317*7d116dccSCC Ma 			mmio_write_32(SPM_CA15_CPU1_IRQ_MASK, 1);
318*7d116dccSCC Ma 			mmio_write_32(SPM_SLEEP_CA15_WFI1_EN, 1);
319*7d116dccSCC Ma 			break;
320*7d116dccSCC Ma 		case 2:
321*7d116dccSCC Ma 			mmio_write_32(SPM_CA15_CPU2_IRQ_MASK, 1);
322*7d116dccSCC Ma 			mmio_write_32(SPM_SLEEP_CA15_WFI2_EN, 1);
323*7d116dccSCC Ma 			break;
324*7d116dccSCC Ma 		case 3:
325*7d116dccSCC Ma 			mmio_write_32(SPM_CA15_CPU3_IRQ_MASK, 1);
326*7d116dccSCC Ma 			mmio_write_32(SPM_SLEEP_CA15_WFI3_EN, 1);
327*7d116dccSCC Ma 			break;
328*7d116dccSCC Ma 		default:
329*7d116dccSCC Ma 			break;
330*7d116dccSCC Ma 		}
331*7d116dccSCC Ma 	} else {
332*7d116dccSCC Ma 		switch (core_id_val) {
333*7d116dccSCC Ma 		case 0:
334*7d116dccSCC Ma 			mmio_write_32(SPM_CA7_CPU0_IRQ_MASK, 1);
335*7d116dccSCC Ma 			mmio_write_32(SPM_SLEEP_CA7_WFI0_EN, 1);
336*7d116dccSCC Ma 			break;
337*7d116dccSCC Ma 		case 1:
338*7d116dccSCC Ma 			mmio_write_32(SPM_CA7_CPU1_IRQ_MASK, 1);
339*7d116dccSCC Ma 			mmio_write_32(SPM_SLEEP_CA7_WFI1_EN, 1);
340*7d116dccSCC Ma 			break;
341*7d116dccSCC Ma 		case 2:
342*7d116dccSCC Ma 			mmio_write_32(SPM_CA7_CPU2_IRQ_MASK, 1);
343*7d116dccSCC Ma 			mmio_write_32(SPM_SLEEP_CA7_WFI2_EN, 1);
344*7d116dccSCC Ma 			break;
345*7d116dccSCC Ma 		case 3:
346*7d116dccSCC Ma 			mmio_write_32(SPM_CA7_CPU3_IRQ_MASK, 1);
347*7d116dccSCC Ma 			mmio_write_32(SPM_SLEEP_CA7_WFI3_EN, 1);
348*7d116dccSCC Ma 			break;
349*7d116dccSCC Ma 		default:
350*7d116dccSCC Ma 			break;
351*7d116dccSCC Ma 		}
352*7d116dccSCC Ma 	}
353*7d116dccSCC Ma }
354*7d116dccSCC Ma 
355*7d116dccSCC Ma void spm_mcdi_wfi_sel_leave(unsigned long mpidr)
356*7d116dccSCC Ma {
357*7d116dccSCC Ma 	int core_id_val = mpidr & MPIDR_CPU_MASK;
358*7d116dccSCC Ma 	int cluster_id = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS;
359*7d116dccSCC Ma 
360*7d116dccSCC Ma 	/* SPM WFI Select by core number */
361*7d116dccSCC Ma 	if (cluster_id) {
362*7d116dccSCC Ma 		switch (core_id_val) {
363*7d116dccSCC Ma 		case 0:
364*7d116dccSCC Ma 			mmio_write_32(SPM_SLEEP_CA15_WFI0_EN, 0);
365*7d116dccSCC Ma 			mmio_write_32(SPM_CA15_CPU0_IRQ_MASK, 0);
366*7d116dccSCC Ma 			break;
367*7d116dccSCC Ma 		case 1:
368*7d116dccSCC Ma 			mmio_write_32(SPM_SLEEP_CA15_WFI1_EN, 0);
369*7d116dccSCC Ma 			mmio_write_32(SPM_CA15_CPU1_IRQ_MASK, 0);
370*7d116dccSCC Ma 			break;
371*7d116dccSCC Ma 		case 2:
372*7d116dccSCC Ma 			mmio_write_32(SPM_SLEEP_CA15_WFI2_EN, 0);
373*7d116dccSCC Ma 			mmio_write_32(SPM_CA15_CPU2_IRQ_MASK, 0);
374*7d116dccSCC Ma 			break;
375*7d116dccSCC Ma 		case 3:
376*7d116dccSCC Ma 			mmio_write_32(SPM_SLEEP_CA15_WFI3_EN, 0);
377*7d116dccSCC Ma 			mmio_write_32(SPM_CA15_CPU3_IRQ_MASK, 0);
378*7d116dccSCC Ma 			break;
379*7d116dccSCC Ma 		default:
380*7d116dccSCC Ma 			break;
381*7d116dccSCC Ma 		}
382*7d116dccSCC Ma 	} else {
383*7d116dccSCC Ma 		switch (core_id_val) {
384*7d116dccSCC Ma 		case 0:
385*7d116dccSCC Ma 			mmio_write_32(SPM_SLEEP_CA7_WFI0_EN, 0);
386*7d116dccSCC Ma 			mmio_write_32(SPM_CA7_CPU0_IRQ_MASK, 0);
387*7d116dccSCC Ma 			break;
388*7d116dccSCC Ma 		case 1:
389*7d116dccSCC Ma 			mmio_write_32(SPM_SLEEP_CA7_WFI1_EN, 0);
390*7d116dccSCC Ma 			mmio_write_32(SPM_CA7_CPU1_IRQ_MASK, 0);
391*7d116dccSCC Ma 			break;
392*7d116dccSCC Ma 		case 2:
393*7d116dccSCC Ma 			mmio_write_32(SPM_SLEEP_CA7_WFI2_EN, 0);
394*7d116dccSCC Ma 			mmio_write_32(SPM_CA7_CPU2_IRQ_MASK, 0);
395*7d116dccSCC Ma 			break;
396*7d116dccSCC Ma 		case 3:
397*7d116dccSCC Ma 			mmio_write_32(SPM_SLEEP_CA7_WFI3_EN, 0);
398*7d116dccSCC Ma 			mmio_write_32(SPM_CA7_CPU3_IRQ_MASK, 0);
399*7d116dccSCC Ma 			break;
400*7d116dccSCC Ma 		default:
401*7d116dccSCC Ma 			break;
402*7d116dccSCC Ma 		}
403*7d116dccSCC Ma 	}
404*7d116dccSCC Ma }
405*7d116dccSCC Ma 
406*7d116dccSCC Ma void spm_mcdi_prepare(unsigned long mpidr)
407*7d116dccSCC Ma {
408*7d116dccSCC Ma 	const struct pcm_desc *pcmdesc = spm_mcdi.pcmdesc;
409*7d116dccSCC Ma 	struct pwr_ctrl *pwrctrl = spm_mcdi.pwrctrl;
410*7d116dccSCC Ma 
411*7d116dccSCC Ma 	spm_lock_get();
412*7d116dccSCC Ma 	if (is_mcdi_ready() == 0) {
413*7d116dccSCC Ma 		if (is_hotplug_ready() == 1)
414*7d116dccSCC Ma 			spm_clear_hotplug();
415*7d116dccSCC Ma 		set_pwrctrl_pcm_flags(pwrctrl, 0);
416*7d116dccSCC Ma 		spm_reset_and_init_pcm();
417*7d116dccSCC Ma 		spm_kick_im_to_fetch(pcmdesc);
418*7d116dccSCC Ma 		spm_set_power_control(pwrctrl);
419*7d116dccSCC Ma 		spm_set_wakeup_event(pwrctrl);
420*7d116dccSCC Ma 		spm_kick_pcm_to_run(pwrctrl);
421*7d116dccSCC Ma 		set_mcdi_ready();
422*7d116dccSCC Ma 	}
423*7d116dccSCC Ma 	spm_mcdi_wfi_sel_enter(mpidr);
424*7d116dccSCC Ma 	spm_lock_release();
425*7d116dccSCC Ma }
426*7d116dccSCC Ma 
427*7d116dccSCC Ma void spm_mcdi_finish(unsigned long mpidr)
428*7d116dccSCC Ma {
429*7d116dccSCC Ma 	unsigned long linear_id = platform_get_core_pos(mpidr);
430*7d116dccSCC Ma 
431*7d116dccSCC Ma 	spm_lock_get();
432*7d116dccSCC Ma 	spm_mcdi_wfi_sel_leave(mpidr);
433*7d116dccSCC Ma 	mmio_write_32(SPM_PCM_SW_INT_CLEAR, (0x1 << linear_id));
434*7d116dccSCC Ma 	spm_lock_release();
435*7d116dccSCC Ma }
436