1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #include <bakery_lock.h> 31 #include <debug.h> 32 #include <mmio.h> 33 #include <mt8173_def.h> 34 #include <spm.h> 35 #include <spm_suspend.h> 36 37 /* 38 * System Power Manager (SPM) is a hardware module, which controls cpu or 39 * system power for different power scenarios using different firmware, i.e., 40 * - spm_hotplug.c for cpu power control in cpu hotplug flow. 41 * - spm_mcdi.c for cpu power control in cpu idle power saving state. 42 * - spm_suspend.c for system power control in system suspend scenario. 43 * 44 * This file provide utility functions common to hotplug, mcdi(idle), suspend 45 * power scenarios. A bakery lock (software lock) is incoporated to protect 46 * certain critical sections to avoid kicking different SPM firmware 47 * concurrently. 48 */ 49 50 #define SPM_SYSCLK_SETTLE 128 /* 3.9ms */ 51 52 #if DEBUG 53 static int spm_dormant_sta = CPU_DORMANT_RESET; 54 #endif 55 56 static bakery_lock_t spm_lock __attribute__ ((section("tzfw_coherent_mem"))); 57 static int spm_hotplug_ready __attribute__ ((section("tzfw_coherent_mem"))); 58 static int spm_mcdi_ready __attribute__ ((section("tzfw_coherent_mem"))); 59 static int spm_suspend_ready __attribute__ ((section("tzfw_coherent_mem"))); 60 61 void spm_lock_init(void) 62 { 63 bakery_lock_init(&spm_lock); 64 } 65 66 void spm_lock_get(void) 67 { 68 bakery_lock_get(&spm_lock); 69 } 70 71 void spm_lock_release(void) 72 { 73 bakery_lock_release(&spm_lock); 74 } 75 76 int is_mcdi_ready(void) 77 { 78 return spm_mcdi_ready; 79 } 80 81 int is_hotplug_ready(void) 82 { 83 return spm_hotplug_ready; 84 } 85 86 int is_suspend_ready(void) 87 { 88 return spm_suspend_ready; 89 } 90 91 void set_mcdi_ready(void) 92 { 93 spm_mcdi_ready = 1; 94 spm_hotplug_ready = 0; 95 spm_suspend_ready = 0; 96 } 97 98 void set_hotplug_ready(void) 99 { 100 spm_mcdi_ready = 0; 101 spm_hotplug_ready = 1; 102 spm_suspend_ready = 0; 103 } 104 105 void set_suspend_ready(void) 106 { 107 spm_mcdi_ready = 0; 108 spm_hotplug_ready = 0; 109 spm_suspend_ready = 1; 110 } 111 112 void clear_all_ready(void) 113 { 114 spm_mcdi_ready = 0; 115 spm_hotplug_ready = 0; 116 spm_suspend_ready = 0; 117 } 118 119 void spm_register_init(void) 120 { 121 mmio_write_32(SPM_POWERON_CONFIG_SET, SPM_REGWR_CFG_KEY | SPM_REGWR_EN); 122 123 mmio_write_32(SPM_POWER_ON_VAL0, 0); 124 mmio_write_32(SPM_POWER_ON_VAL1, POWER_ON_VAL1_DEF); 125 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); 126 127 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_PCM_SW_RESET); 128 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY); 129 if (mmio_read_32(SPM_PCM_FSM_STA) != PCM_FSM_STA_DEF) 130 WARN("PCM reset failed\n"); 131 132 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_IM_SLEEP_DVS); 133 mmio_write_32(SPM_PCM_CON1, CON1_CFG_KEY | CON1_EVENT_LOCK_EN | 134 CON1_SPM_SRAM_ISO_B | CON1_SPM_SRAM_SLP_B | CON1_MIF_APBEN); 135 mmio_write_32(SPM_PCM_IM_PTR, 0); 136 mmio_write_32(SPM_PCM_IM_LEN, 0); 137 138 mmio_write_32(SPM_CLK_CON, CC_SYSCLK0_EN_1 | CC_SYSCLK0_EN_0 | 139 CC_SYSCLK1_EN_0 | CC_SRCLKENA_MASK_0 | CC_CLKSQ1_SEL | 140 CC_CXO32K_RM_EN_MD2 | CC_CXO32K_RM_EN_MD1 | CC_MD32_DCM_EN); 141 142 mmio_write_32(SPM_SLEEP_ISR_MASK, 0xff0c); 143 mmio_write_32(SPM_SLEEP_ISR_STATUS, 0xc); 144 mmio_write_32(SPM_PCM_SW_INT_CLEAR, 0xff); 145 mmio_write_32(SPM_MD32_SRAM_CON, 0xff0); 146 } 147 148 void spm_reset_and_init_pcm(void) 149 { 150 unsigned int con1; 151 int i = 0; 152 153 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_PCM_SW_RESET); 154 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY); 155 while (mmio_read_32(SPM_PCM_FSM_STA) != PCM_FSM_STA_DEF) { 156 i++; 157 if (i > 1000) { 158 i = 0; 159 WARN("PCM reset failed\n"); 160 break; 161 } 162 } 163 164 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_IM_SLEEP_DVS); 165 166 con1 = mmio_read_32(SPM_PCM_CON1) & 167 (CON1_PCM_WDT_WAKE_MODE | CON1_PCM_WDT_EN); 168 mmio_write_32(SPM_PCM_CON1, con1 | CON1_CFG_KEY | CON1_EVENT_LOCK_EN | 169 CON1_SPM_SRAM_ISO_B | CON1_SPM_SRAM_SLP_B | 170 CON1_IM_NONRP_EN | CON1_MIF_APBEN); 171 } 172 173 void spm_init_pcm_register(void) 174 { 175 mmio_write_32(SPM_PCM_REG_DATA_INI, mmio_read_32(SPM_POWER_ON_VAL0)); 176 mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R0); 177 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); 178 179 mmio_write_32(SPM_PCM_REG_DATA_INI, mmio_read_32(SPM_POWER_ON_VAL1)); 180 mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R7); 181 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); 182 } 183 184 void spm_set_power_control(const struct pwr_ctrl *pwrctrl) 185 { 186 mmio_write_32(SPM_AP_STANBY_CON, (!pwrctrl->md32_req_mask << 21) | 187 (!pwrctrl->mfg_req_mask << 17) | 188 (!pwrctrl->disp_req_mask << 16) | 189 (!!pwrctrl->mcusys_idle_mask << 7) | 190 (!!pwrctrl->ca15top_idle_mask << 6) | 191 (!!pwrctrl->ca7top_idle_mask << 5) | 192 (!!pwrctrl->wfi_op << 4)); 193 mmio_write_32(SPM_PCM_SRC_REQ, (!!pwrctrl->pcm_apsrc_req << 0)); 194 mmio_write_32(SPM_PCM_PASR_DPD_2, 0); 195 196 mmio_clrsetbits_32(SPM_CLK_CON, CC_SRCLKENA_MASK_0, 197 (pwrctrl->srclkenai_mask ? CC_SRCLKENA_MASK_0 : 0)); 198 199 mmio_write_32(SPM_SLEEP_CA15_WFI0_EN, !!pwrctrl->ca15_wfi0_en); 200 mmio_write_32(SPM_SLEEP_CA15_WFI1_EN, !!pwrctrl->ca15_wfi1_en); 201 mmio_write_32(SPM_SLEEP_CA15_WFI2_EN, !!pwrctrl->ca15_wfi2_en); 202 mmio_write_32(SPM_SLEEP_CA15_WFI3_EN, !!pwrctrl->ca15_wfi3_en); 203 mmio_write_32(SPM_SLEEP_CA7_WFI0_EN, !!pwrctrl->ca7_wfi0_en); 204 mmio_write_32(SPM_SLEEP_CA7_WFI1_EN, !!pwrctrl->ca7_wfi1_en); 205 mmio_write_32(SPM_SLEEP_CA7_WFI2_EN, !!pwrctrl->ca7_wfi2_en); 206 mmio_write_32(SPM_SLEEP_CA7_WFI3_EN, !!pwrctrl->ca7_wfi3_en); 207 } 208 209 void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) 210 { 211 unsigned int val, mask; 212 213 if (pwrctrl->timer_val_cust == 0) 214 val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX; 215 else 216 val = pwrctrl->timer_val_cust; 217 218 mmio_write_32(SPM_PCM_TIMER_VAL, val); 219 mmio_setbits_32(SPM_PCM_CON1, CON1_CFG_KEY); 220 221 if (pwrctrl->wake_src_cust == 0) 222 mask = pwrctrl->wake_src; 223 else 224 mask = pwrctrl->wake_src_cust; 225 226 if (pwrctrl->syspwreq_mask) 227 mask &= ~WAKE_SRC_SYSPWREQ; 228 229 mmio_write_32(SPM_SLEEP_WAKEUP_EVENT_MASK, ~mask); 230 mmio_write_32(SPM_SLEEP_ISR_MASK, 0xfe04); 231 } 232 233 void spm_get_wakeup_status(struct wake_status *wakesta) 234 { 235 wakesta->assert_pc = mmio_read_32(SPM_PCM_REG_DATA_INI); 236 wakesta->r12 = mmio_read_32(SPM_PCM_REG12_DATA); 237 wakesta->raw_sta = mmio_read_32(SPM_SLEEP_ISR_RAW_STA); 238 wakesta->wake_misc = mmio_read_32(SPM_SLEEP_WAKEUP_MISC); 239 wakesta->timer_out = mmio_read_32(SPM_PCM_TIMER_OUT); 240 wakesta->r13 = mmio_read_32(SPM_PCM_REG13_DATA); 241 wakesta->idle_sta = mmio_read_32(SPM_SLEEP_SUBSYS_IDLE_STA); 242 wakesta->debug_flag = mmio_read_32(SPM_PCM_PASR_DPD_3); 243 wakesta->event_reg = mmio_read_32(SPM_PCM_EVENT_REG_STA); 244 wakesta->isr = mmio_read_32(SPM_SLEEP_ISR_STATUS); 245 } 246 247 void spm_init_event_vector(const struct pcm_desc *pcmdesc) 248 { 249 /* init event vector register */ 250 mmio_write_32(SPM_PCM_EVENT_VECTOR0, pcmdesc->vec0); 251 mmio_write_32(SPM_PCM_EVENT_VECTOR1, pcmdesc->vec1); 252 mmio_write_32(SPM_PCM_EVENT_VECTOR2, pcmdesc->vec2); 253 mmio_write_32(SPM_PCM_EVENT_VECTOR3, pcmdesc->vec3); 254 mmio_write_32(SPM_PCM_EVENT_VECTOR4, pcmdesc->vec4); 255 mmio_write_32(SPM_PCM_EVENT_VECTOR5, pcmdesc->vec5); 256 mmio_write_32(SPM_PCM_EVENT_VECTOR6, pcmdesc->vec6); 257 mmio_write_32(SPM_PCM_EVENT_VECTOR7, pcmdesc->vec7); 258 259 /* event vector will be enabled by PCM itself */ 260 } 261 262 void spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc) 263 { 264 unsigned int ptr = 0, len, con0; 265 266 ptr = (unsigned int)(unsigned long)(pcmdesc->base); 267 len = pcmdesc->size - 1; 268 if (mmio_read_32(SPM_PCM_IM_PTR) != ptr || 269 mmio_read_32(SPM_PCM_IM_LEN) != len || 270 pcmdesc->sess > 2) { 271 mmio_write_32(SPM_PCM_IM_PTR, ptr); 272 mmio_write_32(SPM_PCM_IM_LEN, len); 273 } else { 274 mmio_setbits_32(SPM_PCM_CON1, CON1_CFG_KEY | CON1_IM_SLAVE); 275 } 276 277 /* kick IM to fetch (only toggle IM_KICK) */ 278 con0 = mmio_read_32(SPM_PCM_CON0) & ~(CON0_IM_KICK | CON0_PCM_KICK); 279 mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY | CON0_IM_KICK); 280 mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY); 281 282 /* kick IM to fetch (only toggle PCM_KICK) */ 283 con0 = mmio_read_32(SPM_PCM_CON0) & ~(CON0_IM_KICK | CON0_PCM_KICK); 284 mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY | CON0_PCM_KICK); 285 mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY); 286 } 287 288 void spm_set_sysclk_settle(void) 289 { 290 mmio_write_32(SPM_CLK_SETTLE, SPM_SYSCLK_SETTLE); 291 292 INFO("settle = %u\n", mmio_read_32(SPM_CLK_SETTLE)); 293 } 294 295 void spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl) 296 { 297 unsigned int con1; 298 299 con1 = mmio_read_32(SPM_PCM_CON1) & 300 ~(CON1_PCM_WDT_WAKE_MODE | CON1_PCM_WDT_EN); 301 302 mmio_write_32(SPM_PCM_CON1, CON1_CFG_KEY | con1); 303 304 if (mmio_read_32(SPM_PCM_TIMER_VAL) > PCM_TIMER_MAX) 305 mmio_write_32(SPM_PCM_TIMER_VAL, PCM_TIMER_MAX); 306 307 mmio_write_32(SPM_PCM_WDT_TIMER_VAL, 308 mmio_read_32(SPM_PCM_TIMER_VAL) + PCM_WDT_TIMEOUT); 309 310 mmio_write_32(SPM_PCM_CON1, con1 | CON1_CFG_KEY | CON1_PCM_WDT_EN); 311 mmio_write_32(SPM_PCM_PASR_DPD_0, 0); 312 313 mmio_write_32(SPM_PCM_MAS_PAUSE_MASK, 0xffffffff); 314 mmio_write_32(SPM_PCM_REG_DATA_INI, 0); 315 mmio_clrbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR); 316 317 mmio_write_32(SPM_PCM_FLAGS, pwrctrl->pcm_flags); 318 319 mmio_clrsetbits_32(SPM_CLK_CON, CC_LOCK_INFRA_DCM, 320 (pwrctrl->infra_dcm_lock ? CC_LOCK_INFRA_DCM : 0)); 321 322 mmio_write_32(SPM_PCM_PWR_IO_EN, 323 (pwrctrl->r0_ctrl_en ? PCM_PWRIO_EN_R0 : 0) | 324 (pwrctrl->r7_ctrl_en ? PCM_PWRIO_EN_R7 : 0)); 325 } 326 327 void spm_clean_after_wakeup(void) 328 { 329 mmio_clrsetbits_32(SPM_PCM_CON1, CON1_PCM_WDT_EN, CON1_CFG_KEY); 330 331 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); 332 mmio_write_32(SPM_SLEEP_CPU_WAKEUP_EVENT, 0); 333 mmio_clrsetbits_32(SPM_PCM_CON1, CON1_PCM_TIMER_EN, CON1_CFG_KEY); 334 335 mmio_write_32(SPM_SLEEP_WAKEUP_EVENT_MASK, ~0); 336 mmio_write_32(SPM_SLEEP_ISR_MASK, 0xFF0C); 337 mmio_write_32(SPM_SLEEP_ISR_STATUS, 0xC); 338 mmio_write_32(SPM_PCM_SW_INT_CLEAR, 0xFF); 339 } 340 341 enum wake_reason_t spm_output_wake_reason(struct wake_status *wakesta) 342 { 343 enum wake_reason_t wr; 344 int i; 345 346 wr = WR_UNKNOWN; 347 348 if (wakesta->assert_pc != 0) { 349 ERROR("PCM ASSERT AT %u, r12=0x%x, r13=0x%x, debug_flag=0x%x\n", 350 wakesta->assert_pc, wakesta->r12, wakesta->r13, 351 wakesta->debug_flag); 352 return WR_PCM_ASSERT; 353 } 354 355 if (wakesta->r12 & WAKE_SRC_SPM_MERGE) { 356 if (wakesta->wake_misc & WAKE_MISC_PCM_TIMER) 357 wr = WR_PCM_TIMER; 358 if (wakesta->wake_misc & WAKE_MISC_CPU_WAKE) 359 wr = WR_WAKE_SRC; 360 } 361 362 for (i = 1; i < 32; i++) { 363 if (wakesta->r12 & (1U << i)) 364 wr = WR_WAKE_SRC; 365 } 366 367 if ((wakesta->event_reg & 0x100000) == 0) { 368 INFO("pcm sleep abort!\n"); 369 wr = WR_PCM_ABORT; 370 } 371 372 INFO("timer_out = %u, r12 = 0x%x, r13 = 0x%x, debug_flag = 0x%x\n", 373 wakesta->timer_out, wakesta->r12, wakesta->r13, 374 wakesta->debug_flag); 375 376 INFO("raw_sta = 0x%x, idle_sta = 0x%x, event_reg = 0x%x, isr = 0x%x\n", 377 wakesta->raw_sta, wakesta->idle_sta, wakesta->event_reg, 378 wakesta->isr); 379 380 INFO("dormant state = %d\n", spm_dormant_sta); 381 return wr; 382 } 383 384 void spm_boot_init(void) 385 { 386 /* Only CPU0 is online during boot, initialize cpu online reserve bit */ 387 mmio_write_32(SPM_PCM_RESERVE, 0xFE); 388 spm_lock_init(); 389 spm_register_init(); 390 } 391