1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/debug.h> 8 #include <lib/bakery_lock.h> 9 #include <lib/mmio.h> 10 11 #include <mt8173_def.h> 12 #include <spm.h> 13 #include <spm_suspend.h> 14 15 /* 16 * System Power Manager (SPM) is a hardware module, which controls cpu or 17 * system power for different power scenarios using different firmware, i.e., 18 * - spm_hotplug.c for cpu power control in cpu hotplug flow. 19 * - spm_mcdi.c for cpu power control in cpu idle power saving state. 20 * - spm_suspend.c for system power control in system suspend scenario. 21 * 22 * This file provide utility functions common to hotplug, mcdi(idle), suspend 23 * power scenarios. A bakery lock (software lock) is incoporated to protect 24 * certain critical sections to avoid kicking different SPM firmware 25 * concurrently. 26 */ 27 28 #define SPM_SYSCLK_SETTLE 128 /* 3.9ms */ 29 30 DEFINE_BAKERY_LOCK(spm_lock); 31 32 static int spm_hotplug_ready __section(".tzfw_coherent_mem"); 33 static int spm_mcdi_ready __section(".tzfw_coherent_mem"); 34 static int spm_suspend_ready __section(".tzfw_coherent_mem"); 35 36 void spm_lock_init(void) 37 { 38 bakery_lock_init(&spm_lock); 39 } 40 41 void spm_lock_get(void) 42 { 43 bakery_lock_get(&spm_lock); 44 } 45 46 void spm_lock_release(void) 47 { 48 bakery_lock_release(&spm_lock); 49 } 50 51 int is_mcdi_ready(void) 52 { 53 return spm_mcdi_ready; 54 } 55 56 int is_hotplug_ready(void) 57 { 58 return spm_hotplug_ready; 59 } 60 61 int is_suspend_ready(void) 62 { 63 return spm_suspend_ready; 64 } 65 66 void set_mcdi_ready(void) 67 { 68 spm_mcdi_ready = 1; 69 spm_hotplug_ready = 0; 70 spm_suspend_ready = 0; 71 } 72 73 void set_hotplug_ready(void) 74 { 75 spm_mcdi_ready = 0; 76 spm_hotplug_ready = 1; 77 spm_suspend_ready = 0; 78 } 79 80 void set_suspend_ready(void) 81 { 82 spm_mcdi_ready = 0; 83 spm_hotplug_ready = 0; 84 spm_suspend_ready = 1; 85 } 86 87 void clear_all_ready(void) 88 { 89 spm_mcdi_ready = 0; 90 spm_hotplug_ready = 0; 91 spm_suspend_ready = 0; 92 } 93 94 void spm_register_init(void) 95 { 96 mmio_write_32(SPM_POWERON_CONFIG_SET, SPM_REGWR_CFG_KEY | SPM_REGWR_EN); 97 98 mmio_write_32(SPM_POWER_ON_VAL0, 0); 99 mmio_write_32(SPM_POWER_ON_VAL1, POWER_ON_VAL1_DEF); 100 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); 101 102 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_PCM_SW_RESET); 103 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY); 104 if (mmio_read_32(SPM_PCM_FSM_STA) != PCM_FSM_STA_DEF) 105 WARN("PCM reset failed\n"); 106 107 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_IM_SLEEP_DVS); 108 mmio_write_32(SPM_PCM_CON1, CON1_CFG_KEY | CON1_EVENT_LOCK_EN | 109 CON1_SPM_SRAM_ISO_B | CON1_SPM_SRAM_SLP_B | CON1_MIF_APBEN); 110 mmio_write_32(SPM_PCM_IM_PTR, 0); 111 mmio_write_32(SPM_PCM_IM_LEN, 0); 112 113 mmio_write_32(SPM_CLK_CON, CC_SYSCLK0_EN_1 | CC_SYSCLK0_EN_0 | 114 CC_SYSCLK1_EN_0 | CC_SRCLKENA_MASK_0 | CC_CLKSQ1_SEL | 115 CC_CXO32K_RM_EN_MD2 | CC_CXO32K_RM_EN_MD1 | CC_MD32_DCM_EN); 116 117 mmio_write_32(SPM_SLEEP_ISR_MASK, 0xff0c); 118 mmio_write_32(SPM_SLEEP_ISR_STATUS, 0xc); 119 mmio_write_32(SPM_PCM_SW_INT_CLEAR, 0xff); 120 mmio_write_32(SPM_MD32_SRAM_CON, 0xff0); 121 } 122 123 void spm_reset_and_init_pcm(void) 124 { 125 unsigned int con1; 126 int i = 0; 127 128 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_PCM_SW_RESET); 129 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY); 130 while (mmio_read_32(SPM_PCM_FSM_STA) != PCM_FSM_STA_DEF) { 131 i++; 132 if (i > 1000) { 133 i = 0; 134 WARN("PCM reset failed\n"); 135 break; 136 } 137 } 138 139 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_IM_SLEEP_DVS); 140 141 con1 = mmio_read_32(SPM_PCM_CON1) & 142 (CON1_PCM_WDT_WAKE_MODE | CON1_PCM_WDT_EN); 143 mmio_write_32(SPM_PCM_CON1, con1 | CON1_CFG_KEY | CON1_EVENT_LOCK_EN | 144 CON1_SPM_SRAM_ISO_B | CON1_SPM_SRAM_SLP_B | 145 CON1_IM_NONRP_EN | CON1_MIF_APBEN); 146 } 147 148 void spm_init_pcm_register(void) 149 { 150 mmio_write_32(SPM_PCM_REG_DATA_INI, mmio_read_32(SPM_POWER_ON_VAL0)); 151 mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R0); 152 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); 153 154 mmio_write_32(SPM_PCM_REG_DATA_INI, mmio_read_32(SPM_POWER_ON_VAL1)); 155 mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R7); 156 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); 157 } 158 159 void spm_set_power_control(const struct pwr_ctrl *pwrctrl) 160 { 161 mmio_write_32(SPM_AP_STANBY_CON, (!pwrctrl->md32_req_mask << 21) | 162 (!pwrctrl->mfg_req_mask << 17) | 163 (!pwrctrl->disp_req_mask << 16) | 164 (!!pwrctrl->mcusys_idle_mask << 7) | 165 (!!pwrctrl->ca15top_idle_mask << 6) | 166 (!!pwrctrl->ca7top_idle_mask << 5) | 167 (!!pwrctrl->wfi_op << 4)); 168 mmio_write_32(SPM_PCM_SRC_REQ, (!!pwrctrl->pcm_apsrc_req << 0)); 169 mmio_write_32(SPM_PCM_PASR_DPD_2, 0); 170 171 mmio_clrsetbits_32(SPM_CLK_CON, CC_SRCLKENA_MASK_0, 172 (pwrctrl->srclkenai_mask ? CC_SRCLKENA_MASK_0 : 0)); 173 174 mmio_write_32(SPM_SLEEP_CA15_WFI0_EN, !!pwrctrl->ca15_wfi0_en); 175 mmio_write_32(SPM_SLEEP_CA15_WFI1_EN, !!pwrctrl->ca15_wfi1_en); 176 mmio_write_32(SPM_SLEEP_CA15_WFI2_EN, !!pwrctrl->ca15_wfi2_en); 177 mmio_write_32(SPM_SLEEP_CA15_WFI3_EN, !!pwrctrl->ca15_wfi3_en); 178 mmio_write_32(SPM_SLEEP_CA7_WFI0_EN, !!pwrctrl->ca7_wfi0_en); 179 mmio_write_32(SPM_SLEEP_CA7_WFI1_EN, !!pwrctrl->ca7_wfi1_en); 180 mmio_write_32(SPM_SLEEP_CA7_WFI2_EN, !!pwrctrl->ca7_wfi2_en); 181 mmio_write_32(SPM_SLEEP_CA7_WFI3_EN, !!pwrctrl->ca7_wfi3_en); 182 } 183 184 void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) 185 { 186 unsigned int val, mask; 187 188 if (pwrctrl->timer_val_cust == 0) 189 val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX; 190 else 191 val = pwrctrl->timer_val_cust; 192 193 mmio_write_32(SPM_PCM_TIMER_VAL, val); 194 mmio_setbits_32(SPM_PCM_CON1, CON1_CFG_KEY); 195 196 if (pwrctrl->wake_src_cust == 0) 197 mask = pwrctrl->wake_src; 198 else 199 mask = pwrctrl->wake_src_cust; 200 201 if (pwrctrl->syspwreq_mask) 202 mask &= ~WAKE_SRC_SYSPWREQ; 203 204 mmio_write_32(SPM_SLEEP_WAKEUP_EVENT_MASK, ~mask); 205 mmio_write_32(SPM_SLEEP_ISR_MASK, 0xfe04); 206 } 207 208 void spm_get_wakeup_status(struct wake_status *wakesta) 209 { 210 wakesta->assert_pc = mmio_read_32(SPM_PCM_REG_DATA_INI); 211 wakesta->r12 = mmio_read_32(SPM_PCM_REG12_DATA); 212 wakesta->raw_sta = mmio_read_32(SPM_SLEEP_ISR_RAW_STA); 213 wakesta->wake_misc = mmio_read_32(SPM_SLEEP_WAKEUP_MISC); 214 wakesta->timer_out = mmio_read_32(SPM_PCM_TIMER_OUT); 215 wakesta->r13 = mmio_read_32(SPM_PCM_REG13_DATA); 216 wakesta->idle_sta = mmio_read_32(SPM_SLEEP_SUBSYS_IDLE_STA); 217 wakesta->debug_flag = mmio_read_32(SPM_PCM_PASR_DPD_3); 218 wakesta->event_reg = mmio_read_32(SPM_PCM_EVENT_REG_STA); 219 wakesta->isr = mmio_read_32(SPM_SLEEP_ISR_STATUS); 220 } 221 222 void spm_init_event_vector(const struct pcm_desc *pcmdesc) 223 { 224 /* init event vector register */ 225 mmio_write_32(SPM_PCM_EVENT_VECTOR0, pcmdesc->vec0); 226 mmio_write_32(SPM_PCM_EVENT_VECTOR1, pcmdesc->vec1); 227 mmio_write_32(SPM_PCM_EVENT_VECTOR2, pcmdesc->vec2); 228 mmio_write_32(SPM_PCM_EVENT_VECTOR3, pcmdesc->vec3); 229 mmio_write_32(SPM_PCM_EVENT_VECTOR4, pcmdesc->vec4); 230 mmio_write_32(SPM_PCM_EVENT_VECTOR5, pcmdesc->vec5); 231 mmio_write_32(SPM_PCM_EVENT_VECTOR6, pcmdesc->vec6); 232 mmio_write_32(SPM_PCM_EVENT_VECTOR7, pcmdesc->vec7); 233 234 /* event vector will be enabled by PCM itself */ 235 } 236 237 void spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc) 238 { 239 unsigned int ptr = 0, len, con0; 240 241 ptr = (unsigned int)(unsigned long)(pcmdesc->base); 242 len = pcmdesc->size - 1; 243 if (mmio_read_32(SPM_PCM_IM_PTR) != ptr || 244 mmio_read_32(SPM_PCM_IM_LEN) != len || 245 pcmdesc->sess > 2) { 246 mmio_write_32(SPM_PCM_IM_PTR, ptr); 247 mmio_write_32(SPM_PCM_IM_LEN, len); 248 } else { 249 mmio_setbits_32(SPM_PCM_CON1, CON1_CFG_KEY | CON1_IM_SLAVE); 250 } 251 252 /* kick IM to fetch (only toggle IM_KICK) */ 253 con0 = mmio_read_32(SPM_PCM_CON0) & ~(CON0_IM_KICK | CON0_PCM_KICK); 254 mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY | CON0_IM_KICK); 255 mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY); 256 257 /* kick IM to fetch (only toggle PCM_KICK) */ 258 con0 = mmio_read_32(SPM_PCM_CON0) & ~(CON0_IM_KICK | CON0_PCM_KICK); 259 mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY | CON0_PCM_KICK); 260 mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY); 261 } 262 263 void spm_set_sysclk_settle(void) 264 { 265 mmio_write_32(SPM_CLK_SETTLE, SPM_SYSCLK_SETTLE); 266 267 INFO("settle = %u\n", mmio_read_32(SPM_CLK_SETTLE)); 268 } 269 270 void spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl) 271 { 272 unsigned int con1; 273 274 con1 = mmio_read_32(SPM_PCM_CON1) & 275 ~(CON1_PCM_WDT_WAKE_MODE | CON1_PCM_WDT_EN); 276 277 mmio_write_32(SPM_PCM_CON1, CON1_CFG_KEY | con1); 278 279 if (mmio_read_32(SPM_PCM_TIMER_VAL) > PCM_TIMER_MAX) 280 mmio_write_32(SPM_PCM_TIMER_VAL, PCM_TIMER_MAX); 281 282 mmio_write_32(SPM_PCM_WDT_TIMER_VAL, 283 mmio_read_32(SPM_PCM_TIMER_VAL) + PCM_WDT_TIMEOUT); 284 285 mmio_write_32(SPM_PCM_CON1, con1 | CON1_CFG_KEY | CON1_PCM_WDT_EN); 286 mmio_write_32(SPM_PCM_PASR_DPD_0, 0); 287 288 mmio_write_32(SPM_PCM_MAS_PAUSE_MASK, 0xffffffff); 289 mmio_write_32(SPM_PCM_REG_DATA_INI, 0); 290 mmio_clrbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR); 291 292 mmio_write_32(SPM_PCM_FLAGS, pwrctrl->pcm_flags); 293 294 mmio_clrsetbits_32(SPM_CLK_CON, CC_LOCK_INFRA_DCM, 295 (pwrctrl->infra_dcm_lock ? CC_LOCK_INFRA_DCM : 0)); 296 297 mmio_write_32(SPM_PCM_PWR_IO_EN, 298 (pwrctrl->r0_ctrl_en ? PCM_PWRIO_EN_R0 : 0) | 299 (pwrctrl->r7_ctrl_en ? PCM_PWRIO_EN_R7 : 0)); 300 } 301 302 void spm_clean_after_wakeup(void) 303 { 304 mmio_clrsetbits_32(SPM_PCM_CON1, CON1_PCM_WDT_EN, CON1_CFG_KEY); 305 306 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); 307 mmio_write_32(SPM_SLEEP_CPU_WAKEUP_EVENT, 0); 308 mmio_clrsetbits_32(SPM_PCM_CON1, CON1_PCM_TIMER_EN, CON1_CFG_KEY); 309 310 mmio_write_32(SPM_SLEEP_WAKEUP_EVENT_MASK, ~0); 311 mmio_write_32(SPM_SLEEP_ISR_MASK, 0xFF0C); 312 mmio_write_32(SPM_SLEEP_ISR_STATUS, 0xC); 313 mmio_write_32(SPM_PCM_SW_INT_CLEAR, 0xFF); 314 } 315 316 enum wake_reason_t spm_output_wake_reason(struct wake_status *wakesta) 317 { 318 enum wake_reason_t wr; 319 int i; 320 321 wr = WR_UNKNOWN; 322 323 if (wakesta->assert_pc != 0) { 324 ERROR("PCM ASSERT AT %u, r12=0x%x, r13=0x%x, debug_flag=0x%x\n", 325 wakesta->assert_pc, wakesta->r12, wakesta->r13, 326 wakesta->debug_flag); 327 return WR_PCM_ASSERT; 328 } 329 330 if (wakesta->r12 & WAKE_SRC_SPM_MERGE) { 331 if (wakesta->wake_misc & WAKE_MISC_PCM_TIMER) 332 wr = WR_PCM_TIMER; 333 if (wakesta->wake_misc & WAKE_MISC_CPU_WAKE) 334 wr = WR_WAKE_SRC; 335 } 336 337 for (i = 1; i < 32; i++) { 338 if (wakesta->r12 & (1U << i)) 339 wr = WR_WAKE_SRC; 340 } 341 342 if ((wakesta->event_reg & 0x100000) == 0) { 343 INFO("pcm sleep abort!\n"); 344 wr = WR_PCM_ABORT; 345 } 346 347 INFO("timer_out = %u, r12 = 0x%x, r13 = 0x%x, debug_flag = 0x%x\n", 348 wakesta->timer_out, wakesta->r12, wakesta->r13, 349 wakesta->debug_flag); 350 351 INFO("raw_sta = 0x%x, idle_sta = 0x%x, event_reg = 0x%x, isr = 0x%x\n", 352 wakesta->raw_sta, wakesta->idle_sta, wakesta->event_reg, 353 wakesta->isr); 354 355 return wr; 356 } 357 358 void spm_boot_init(void) 359 { 360 /* set spm transaction to secure mode */ 361 mmio_write_32(DEVAPC0_APC_CON, 0x0); 362 mmio_write_32(DEVAPC0_MAS_SEC_0, 0x200); 363 364 /* Only CPU0 is online during boot, initialize cpu online reserve bit */ 365 mmio_write_32(SPM_PCM_RESERVE, 0xFE); 366 mmio_clrbits_32(AP_PLL_CON3, 0xFFFFF); 367 mmio_clrbits_32(AP_PLL_CON4, 0xF); 368 spm_lock_init(); 369 spm_register_init(); 370 } 371