1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #include <bakery_lock.h> 31 #include <debug.h> 32 #include <mmio.h> 33 #include <mt8173_def.h> 34 #include <spm.h> 35 #include <spm_suspend.h> 36 37 /* 38 * System Power Manager (SPM) is a hardware module, which controls cpu or 39 * system power for different power scenarios using different firmware, i.e., 40 * - spm_hotplug.c for cpu power control in cpu hotplug flow. 41 * - spm_mcdi.c for cpu power control in cpu idle power saving state. 42 * - spm_suspend.c for system power control in system suspend scenario. 43 * 44 * This file provide utility functions common to hotplug, mcdi(idle), suspend 45 * power scenarios. A bakery lock (software lock) is incoporated to protect 46 * certain critical sections to avoid kicking different SPM firmware 47 * concurrently. 48 */ 49 50 #define SPM_SYSCLK_SETTLE 128 /* 3.9ms */ 51 52 DEFINE_BAKERY_LOCK(spm_lock); 53 54 static int spm_hotplug_ready __section("tzfw_coherent_mem"); 55 static int spm_mcdi_ready __section("tzfw_coherent_mem"); 56 static int spm_suspend_ready __section("tzfw_coherent_mem"); 57 58 void spm_lock_init(void) 59 { 60 bakery_lock_init(&spm_lock); 61 } 62 63 void spm_lock_get(void) 64 { 65 bakery_lock_get(&spm_lock); 66 } 67 68 void spm_lock_release(void) 69 { 70 bakery_lock_release(&spm_lock); 71 } 72 73 int is_mcdi_ready(void) 74 { 75 return spm_mcdi_ready; 76 } 77 78 int is_hotplug_ready(void) 79 { 80 return spm_hotplug_ready; 81 } 82 83 int is_suspend_ready(void) 84 { 85 return spm_suspend_ready; 86 } 87 88 void set_mcdi_ready(void) 89 { 90 spm_mcdi_ready = 1; 91 spm_hotplug_ready = 0; 92 spm_suspend_ready = 0; 93 } 94 95 void set_hotplug_ready(void) 96 { 97 spm_mcdi_ready = 0; 98 spm_hotplug_ready = 1; 99 spm_suspend_ready = 0; 100 } 101 102 void set_suspend_ready(void) 103 { 104 spm_mcdi_ready = 0; 105 spm_hotplug_ready = 0; 106 spm_suspend_ready = 1; 107 } 108 109 void clear_all_ready(void) 110 { 111 spm_mcdi_ready = 0; 112 spm_hotplug_ready = 0; 113 spm_suspend_ready = 0; 114 } 115 116 void spm_register_init(void) 117 { 118 mmio_write_32(SPM_POWERON_CONFIG_SET, SPM_REGWR_CFG_KEY | SPM_REGWR_EN); 119 120 mmio_write_32(SPM_POWER_ON_VAL0, 0); 121 mmio_write_32(SPM_POWER_ON_VAL1, POWER_ON_VAL1_DEF); 122 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); 123 124 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_PCM_SW_RESET); 125 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY); 126 if (mmio_read_32(SPM_PCM_FSM_STA) != PCM_FSM_STA_DEF) 127 WARN("PCM reset failed\n"); 128 129 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_IM_SLEEP_DVS); 130 mmio_write_32(SPM_PCM_CON1, CON1_CFG_KEY | CON1_EVENT_LOCK_EN | 131 CON1_SPM_SRAM_ISO_B | CON1_SPM_SRAM_SLP_B | CON1_MIF_APBEN); 132 mmio_write_32(SPM_PCM_IM_PTR, 0); 133 mmio_write_32(SPM_PCM_IM_LEN, 0); 134 135 mmio_write_32(SPM_CLK_CON, CC_SYSCLK0_EN_1 | CC_SYSCLK0_EN_0 | 136 CC_SYSCLK1_EN_0 | CC_SRCLKENA_MASK_0 | CC_CLKSQ1_SEL | 137 CC_CXO32K_RM_EN_MD2 | CC_CXO32K_RM_EN_MD1 | CC_MD32_DCM_EN); 138 139 mmio_write_32(SPM_SLEEP_ISR_MASK, 0xff0c); 140 mmio_write_32(SPM_SLEEP_ISR_STATUS, 0xc); 141 mmio_write_32(SPM_PCM_SW_INT_CLEAR, 0xff); 142 mmio_write_32(SPM_MD32_SRAM_CON, 0xff0); 143 } 144 145 void spm_reset_and_init_pcm(void) 146 { 147 unsigned int con1; 148 int i = 0; 149 150 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_PCM_SW_RESET); 151 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY); 152 while (mmio_read_32(SPM_PCM_FSM_STA) != PCM_FSM_STA_DEF) { 153 i++; 154 if (i > 1000) { 155 i = 0; 156 WARN("PCM reset failed\n"); 157 break; 158 } 159 } 160 161 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_IM_SLEEP_DVS); 162 163 con1 = mmio_read_32(SPM_PCM_CON1) & 164 (CON1_PCM_WDT_WAKE_MODE | CON1_PCM_WDT_EN); 165 mmio_write_32(SPM_PCM_CON1, con1 | CON1_CFG_KEY | CON1_EVENT_LOCK_EN | 166 CON1_SPM_SRAM_ISO_B | CON1_SPM_SRAM_SLP_B | 167 CON1_IM_NONRP_EN | CON1_MIF_APBEN); 168 } 169 170 void spm_init_pcm_register(void) 171 { 172 mmio_write_32(SPM_PCM_REG_DATA_INI, mmio_read_32(SPM_POWER_ON_VAL0)); 173 mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R0); 174 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); 175 176 mmio_write_32(SPM_PCM_REG_DATA_INI, mmio_read_32(SPM_POWER_ON_VAL1)); 177 mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R7); 178 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); 179 } 180 181 void spm_set_power_control(const struct pwr_ctrl *pwrctrl) 182 { 183 mmio_write_32(SPM_AP_STANBY_CON, (!pwrctrl->md32_req_mask << 21) | 184 (!pwrctrl->mfg_req_mask << 17) | 185 (!pwrctrl->disp_req_mask << 16) | 186 (!!pwrctrl->mcusys_idle_mask << 7) | 187 (!!pwrctrl->ca15top_idle_mask << 6) | 188 (!!pwrctrl->ca7top_idle_mask << 5) | 189 (!!pwrctrl->wfi_op << 4)); 190 mmio_write_32(SPM_PCM_SRC_REQ, (!!pwrctrl->pcm_apsrc_req << 0)); 191 mmio_write_32(SPM_PCM_PASR_DPD_2, 0); 192 193 mmio_clrsetbits_32(SPM_CLK_CON, CC_SRCLKENA_MASK_0, 194 (pwrctrl->srclkenai_mask ? CC_SRCLKENA_MASK_0 : 0)); 195 196 mmio_write_32(SPM_SLEEP_CA15_WFI0_EN, !!pwrctrl->ca15_wfi0_en); 197 mmio_write_32(SPM_SLEEP_CA15_WFI1_EN, !!pwrctrl->ca15_wfi1_en); 198 mmio_write_32(SPM_SLEEP_CA15_WFI2_EN, !!pwrctrl->ca15_wfi2_en); 199 mmio_write_32(SPM_SLEEP_CA15_WFI3_EN, !!pwrctrl->ca15_wfi3_en); 200 mmio_write_32(SPM_SLEEP_CA7_WFI0_EN, !!pwrctrl->ca7_wfi0_en); 201 mmio_write_32(SPM_SLEEP_CA7_WFI1_EN, !!pwrctrl->ca7_wfi1_en); 202 mmio_write_32(SPM_SLEEP_CA7_WFI2_EN, !!pwrctrl->ca7_wfi2_en); 203 mmio_write_32(SPM_SLEEP_CA7_WFI3_EN, !!pwrctrl->ca7_wfi3_en); 204 } 205 206 void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) 207 { 208 unsigned int val, mask; 209 210 if (pwrctrl->timer_val_cust == 0) 211 val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX; 212 else 213 val = pwrctrl->timer_val_cust; 214 215 mmio_write_32(SPM_PCM_TIMER_VAL, val); 216 mmio_setbits_32(SPM_PCM_CON1, CON1_CFG_KEY); 217 218 if (pwrctrl->wake_src_cust == 0) 219 mask = pwrctrl->wake_src; 220 else 221 mask = pwrctrl->wake_src_cust; 222 223 if (pwrctrl->syspwreq_mask) 224 mask &= ~WAKE_SRC_SYSPWREQ; 225 226 mmio_write_32(SPM_SLEEP_WAKEUP_EVENT_MASK, ~mask); 227 mmio_write_32(SPM_SLEEP_ISR_MASK, 0xfe04); 228 } 229 230 void spm_get_wakeup_status(struct wake_status *wakesta) 231 { 232 wakesta->assert_pc = mmio_read_32(SPM_PCM_REG_DATA_INI); 233 wakesta->r12 = mmio_read_32(SPM_PCM_REG12_DATA); 234 wakesta->raw_sta = mmio_read_32(SPM_SLEEP_ISR_RAW_STA); 235 wakesta->wake_misc = mmio_read_32(SPM_SLEEP_WAKEUP_MISC); 236 wakesta->timer_out = mmio_read_32(SPM_PCM_TIMER_OUT); 237 wakesta->r13 = mmio_read_32(SPM_PCM_REG13_DATA); 238 wakesta->idle_sta = mmio_read_32(SPM_SLEEP_SUBSYS_IDLE_STA); 239 wakesta->debug_flag = mmio_read_32(SPM_PCM_PASR_DPD_3); 240 wakesta->event_reg = mmio_read_32(SPM_PCM_EVENT_REG_STA); 241 wakesta->isr = mmio_read_32(SPM_SLEEP_ISR_STATUS); 242 } 243 244 void spm_init_event_vector(const struct pcm_desc *pcmdesc) 245 { 246 /* init event vector register */ 247 mmio_write_32(SPM_PCM_EVENT_VECTOR0, pcmdesc->vec0); 248 mmio_write_32(SPM_PCM_EVENT_VECTOR1, pcmdesc->vec1); 249 mmio_write_32(SPM_PCM_EVENT_VECTOR2, pcmdesc->vec2); 250 mmio_write_32(SPM_PCM_EVENT_VECTOR3, pcmdesc->vec3); 251 mmio_write_32(SPM_PCM_EVENT_VECTOR4, pcmdesc->vec4); 252 mmio_write_32(SPM_PCM_EVENT_VECTOR5, pcmdesc->vec5); 253 mmio_write_32(SPM_PCM_EVENT_VECTOR6, pcmdesc->vec6); 254 mmio_write_32(SPM_PCM_EVENT_VECTOR7, pcmdesc->vec7); 255 256 /* event vector will be enabled by PCM itself */ 257 } 258 259 void spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc) 260 { 261 unsigned int ptr = 0, len, con0; 262 263 ptr = (unsigned int)(unsigned long)(pcmdesc->base); 264 len = pcmdesc->size - 1; 265 if (mmio_read_32(SPM_PCM_IM_PTR) != ptr || 266 mmio_read_32(SPM_PCM_IM_LEN) != len || 267 pcmdesc->sess > 2) { 268 mmio_write_32(SPM_PCM_IM_PTR, ptr); 269 mmio_write_32(SPM_PCM_IM_LEN, len); 270 } else { 271 mmio_setbits_32(SPM_PCM_CON1, CON1_CFG_KEY | CON1_IM_SLAVE); 272 } 273 274 /* kick IM to fetch (only toggle IM_KICK) */ 275 con0 = mmio_read_32(SPM_PCM_CON0) & ~(CON0_IM_KICK | CON0_PCM_KICK); 276 mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY | CON0_IM_KICK); 277 mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY); 278 279 /* kick IM to fetch (only toggle PCM_KICK) */ 280 con0 = mmio_read_32(SPM_PCM_CON0) & ~(CON0_IM_KICK | CON0_PCM_KICK); 281 mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY | CON0_PCM_KICK); 282 mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY); 283 } 284 285 void spm_set_sysclk_settle(void) 286 { 287 mmio_write_32(SPM_CLK_SETTLE, SPM_SYSCLK_SETTLE); 288 289 INFO("settle = %u\n", mmio_read_32(SPM_CLK_SETTLE)); 290 } 291 292 void spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl) 293 { 294 unsigned int con1; 295 296 con1 = mmio_read_32(SPM_PCM_CON1) & 297 ~(CON1_PCM_WDT_WAKE_MODE | CON1_PCM_WDT_EN); 298 299 mmio_write_32(SPM_PCM_CON1, CON1_CFG_KEY | con1); 300 301 if (mmio_read_32(SPM_PCM_TIMER_VAL) > PCM_TIMER_MAX) 302 mmio_write_32(SPM_PCM_TIMER_VAL, PCM_TIMER_MAX); 303 304 mmio_write_32(SPM_PCM_WDT_TIMER_VAL, 305 mmio_read_32(SPM_PCM_TIMER_VAL) + PCM_WDT_TIMEOUT); 306 307 mmio_write_32(SPM_PCM_CON1, con1 | CON1_CFG_KEY | CON1_PCM_WDT_EN); 308 mmio_write_32(SPM_PCM_PASR_DPD_0, 0); 309 310 mmio_write_32(SPM_PCM_MAS_PAUSE_MASK, 0xffffffff); 311 mmio_write_32(SPM_PCM_REG_DATA_INI, 0); 312 mmio_clrbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR); 313 314 mmio_write_32(SPM_PCM_FLAGS, pwrctrl->pcm_flags); 315 316 mmio_clrsetbits_32(SPM_CLK_CON, CC_LOCK_INFRA_DCM, 317 (pwrctrl->infra_dcm_lock ? CC_LOCK_INFRA_DCM : 0)); 318 319 mmio_write_32(SPM_PCM_PWR_IO_EN, 320 (pwrctrl->r0_ctrl_en ? PCM_PWRIO_EN_R0 : 0) | 321 (pwrctrl->r7_ctrl_en ? PCM_PWRIO_EN_R7 : 0)); 322 } 323 324 void spm_clean_after_wakeup(void) 325 { 326 mmio_clrsetbits_32(SPM_PCM_CON1, CON1_PCM_WDT_EN, CON1_CFG_KEY); 327 328 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); 329 mmio_write_32(SPM_SLEEP_CPU_WAKEUP_EVENT, 0); 330 mmio_clrsetbits_32(SPM_PCM_CON1, CON1_PCM_TIMER_EN, CON1_CFG_KEY); 331 332 mmio_write_32(SPM_SLEEP_WAKEUP_EVENT_MASK, ~0); 333 mmio_write_32(SPM_SLEEP_ISR_MASK, 0xFF0C); 334 mmio_write_32(SPM_SLEEP_ISR_STATUS, 0xC); 335 mmio_write_32(SPM_PCM_SW_INT_CLEAR, 0xFF); 336 } 337 338 enum wake_reason_t spm_output_wake_reason(struct wake_status *wakesta) 339 { 340 enum wake_reason_t wr; 341 int i; 342 343 wr = WR_UNKNOWN; 344 345 if (wakesta->assert_pc != 0) { 346 ERROR("PCM ASSERT AT %u, r12=0x%x, r13=0x%x, debug_flag=0x%x\n", 347 wakesta->assert_pc, wakesta->r12, wakesta->r13, 348 wakesta->debug_flag); 349 return WR_PCM_ASSERT; 350 } 351 352 if (wakesta->r12 & WAKE_SRC_SPM_MERGE) { 353 if (wakesta->wake_misc & WAKE_MISC_PCM_TIMER) 354 wr = WR_PCM_TIMER; 355 if (wakesta->wake_misc & WAKE_MISC_CPU_WAKE) 356 wr = WR_WAKE_SRC; 357 } 358 359 for (i = 1; i < 32; i++) { 360 if (wakesta->r12 & (1U << i)) 361 wr = WR_WAKE_SRC; 362 } 363 364 if ((wakesta->event_reg & 0x100000) == 0) { 365 INFO("pcm sleep abort!\n"); 366 wr = WR_PCM_ABORT; 367 } 368 369 INFO("timer_out = %u, r12 = 0x%x, r13 = 0x%x, debug_flag = 0x%x\n", 370 wakesta->timer_out, wakesta->r12, wakesta->r13, 371 wakesta->debug_flag); 372 373 INFO("raw_sta = 0x%x, idle_sta = 0x%x, event_reg = 0x%x, isr = 0x%x\n", 374 wakesta->raw_sta, wakesta->idle_sta, wakesta->event_reg, 375 wakesta->isr); 376 377 return wr; 378 } 379 380 void spm_boot_init(void) 381 { 382 /* set spm transaction to secure mode */ 383 mmio_write_32(DEVAPC0_APC_CON, 0x0); 384 mmio_write_32(DEVAPC0_MAS_SEC_0, 0x200); 385 386 /* Only CPU0 is online during boot, initialize cpu online reserve bit */ 387 mmio_write_32(SPM_PCM_RESERVE, 0xFE); 388 mmio_clrbits_32(AP_PLL_CON3, 0xFFFFF); 389 mmio_clrbits_32(AP_PLL_CON4, 0xF); 390 spm_lock_init(); 391 spm_register_init(); 392 } 393