1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #include <bakery_lock.h> 31 #include <debug.h> 32 #include <mmio.h> 33 #include <mt8173_def.h> 34 #include <spm.h> 35 #include <spm_suspend.h> 36 37 /* 38 * System Power Manager (SPM) is a hardware module, which controls cpu or 39 * system power for different power scenarios using different firmware, i.e., 40 * - spm_hotplug.c for cpu power control in cpu hotplug flow. 41 * - spm_mcdi.c for cpu power control in cpu idle power saving state. 42 * - spm_suspend.c for system power control in system suspend scenario. 43 * 44 * This file provide utility functions common to hotplug, mcdi(idle), suspend 45 * power scenarios. A bakery lock (software lock) is incoporated to protect 46 * certain critical sections to avoid kicking different SPM firmware 47 * concurrently. 48 */ 49 50 #define SPM_SYSCLK_SETTLE 128 /* 3.9ms */ 51 52 #if DEBUG 53 static int spm_dormant_sta = CPU_DORMANT_RESET; 54 #endif 55 56 DEFINE_BAKERY_LOCK(spm_lock); 57 58 static int spm_hotplug_ready __section("tzfw_coherent_mem"); 59 static int spm_mcdi_ready __section("tzfw_coherent_mem"); 60 static int spm_suspend_ready __section("tzfw_coherent_mem"); 61 62 void spm_lock_init(void) 63 { 64 bakery_lock_init(&spm_lock); 65 } 66 67 void spm_lock_get(void) 68 { 69 bakery_lock_get(&spm_lock); 70 } 71 72 void spm_lock_release(void) 73 { 74 bakery_lock_release(&spm_lock); 75 } 76 77 int is_mcdi_ready(void) 78 { 79 return spm_mcdi_ready; 80 } 81 82 int is_hotplug_ready(void) 83 { 84 return spm_hotplug_ready; 85 } 86 87 int is_suspend_ready(void) 88 { 89 return spm_suspend_ready; 90 } 91 92 void set_mcdi_ready(void) 93 { 94 spm_mcdi_ready = 1; 95 spm_hotplug_ready = 0; 96 spm_suspend_ready = 0; 97 } 98 99 void set_hotplug_ready(void) 100 { 101 spm_mcdi_ready = 0; 102 spm_hotplug_ready = 1; 103 spm_suspend_ready = 0; 104 } 105 106 void set_suspend_ready(void) 107 { 108 spm_mcdi_ready = 0; 109 spm_hotplug_ready = 0; 110 spm_suspend_ready = 1; 111 } 112 113 void clear_all_ready(void) 114 { 115 spm_mcdi_ready = 0; 116 spm_hotplug_ready = 0; 117 spm_suspend_ready = 0; 118 } 119 120 void spm_register_init(void) 121 { 122 mmio_write_32(SPM_POWERON_CONFIG_SET, SPM_REGWR_CFG_KEY | SPM_REGWR_EN); 123 124 mmio_write_32(SPM_POWER_ON_VAL0, 0); 125 mmio_write_32(SPM_POWER_ON_VAL1, POWER_ON_VAL1_DEF); 126 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); 127 128 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_PCM_SW_RESET); 129 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY); 130 if (mmio_read_32(SPM_PCM_FSM_STA) != PCM_FSM_STA_DEF) 131 WARN("PCM reset failed\n"); 132 133 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_IM_SLEEP_DVS); 134 mmio_write_32(SPM_PCM_CON1, CON1_CFG_KEY | CON1_EVENT_LOCK_EN | 135 CON1_SPM_SRAM_ISO_B | CON1_SPM_SRAM_SLP_B | CON1_MIF_APBEN); 136 mmio_write_32(SPM_PCM_IM_PTR, 0); 137 mmio_write_32(SPM_PCM_IM_LEN, 0); 138 139 mmio_write_32(SPM_CLK_CON, CC_SYSCLK0_EN_1 | CC_SYSCLK0_EN_0 | 140 CC_SYSCLK1_EN_0 | CC_SRCLKENA_MASK_0 | CC_CLKSQ1_SEL | 141 CC_CXO32K_RM_EN_MD2 | CC_CXO32K_RM_EN_MD1 | CC_MD32_DCM_EN); 142 143 mmio_write_32(SPM_SLEEP_ISR_MASK, 0xff0c); 144 mmio_write_32(SPM_SLEEP_ISR_STATUS, 0xc); 145 mmio_write_32(SPM_PCM_SW_INT_CLEAR, 0xff); 146 mmio_write_32(SPM_MD32_SRAM_CON, 0xff0); 147 } 148 149 void spm_reset_and_init_pcm(void) 150 { 151 unsigned int con1; 152 int i = 0; 153 154 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_PCM_SW_RESET); 155 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY); 156 while (mmio_read_32(SPM_PCM_FSM_STA) != PCM_FSM_STA_DEF) { 157 i++; 158 if (i > 1000) { 159 i = 0; 160 WARN("PCM reset failed\n"); 161 break; 162 } 163 } 164 165 mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_IM_SLEEP_DVS); 166 167 con1 = mmio_read_32(SPM_PCM_CON1) & 168 (CON1_PCM_WDT_WAKE_MODE | CON1_PCM_WDT_EN); 169 mmio_write_32(SPM_PCM_CON1, con1 | CON1_CFG_KEY | CON1_EVENT_LOCK_EN | 170 CON1_SPM_SRAM_ISO_B | CON1_SPM_SRAM_SLP_B | 171 CON1_IM_NONRP_EN | CON1_MIF_APBEN); 172 } 173 174 void spm_init_pcm_register(void) 175 { 176 mmio_write_32(SPM_PCM_REG_DATA_INI, mmio_read_32(SPM_POWER_ON_VAL0)); 177 mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R0); 178 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); 179 180 mmio_write_32(SPM_PCM_REG_DATA_INI, mmio_read_32(SPM_POWER_ON_VAL1)); 181 mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R7); 182 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); 183 } 184 185 void spm_set_power_control(const struct pwr_ctrl *pwrctrl) 186 { 187 mmio_write_32(SPM_AP_STANBY_CON, (!pwrctrl->md32_req_mask << 21) | 188 (!pwrctrl->mfg_req_mask << 17) | 189 (!pwrctrl->disp_req_mask << 16) | 190 (!!pwrctrl->mcusys_idle_mask << 7) | 191 (!!pwrctrl->ca15top_idle_mask << 6) | 192 (!!pwrctrl->ca7top_idle_mask << 5) | 193 (!!pwrctrl->wfi_op << 4)); 194 mmio_write_32(SPM_PCM_SRC_REQ, (!!pwrctrl->pcm_apsrc_req << 0)); 195 mmio_write_32(SPM_PCM_PASR_DPD_2, 0); 196 197 mmio_clrsetbits_32(SPM_CLK_CON, CC_SRCLKENA_MASK_0, 198 (pwrctrl->srclkenai_mask ? CC_SRCLKENA_MASK_0 : 0)); 199 200 mmio_write_32(SPM_SLEEP_CA15_WFI0_EN, !!pwrctrl->ca15_wfi0_en); 201 mmio_write_32(SPM_SLEEP_CA15_WFI1_EN, !!pwrctrl->ca15_wfi1_en); 202 mmio_write_32(SPM_SLEEP_CA15_WFI2_EN, !!pwrctrl->ca15_wfi2_en); 203 mmio_write_32(SPM_SLEEP_CA15_WFI3_EN, !!pwrctrl->ca15_wfi3_en); 204 mmio_write_32(SPM_SLEEP_CA7_WFI0_EN, !!pwrctrl->ca7_wfi0_en); 205 mmio_write_32(SPM_SLEEP_CA7_WFI1_EN, !!pwrctrl->ca7_wfi1_en); 206 mmio_write_32(SPM_SLEEP_CA7_WFI2_EN, !!pwrctrl->ca7_wfi2_en); 207 mmio_write_32(SPM_SLEEP_CA7_WFI3_EN, !!pwrctrl->ca7_wfi3_en); 208 } 209 210 void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) 211 { 212 unsigned int val, mask; 213 214 if (pwrctrl->timer_val_cust == 0) 215 val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX; 216 else 217 val = pwrctrl->timer_val_cust; 218 219 mmio_write_32(SPM_PCM_TIMER_VAL, val); 220 mmio_setbits_32(SPM_PCM_CON1, CON1_CFG_KEY); 221 222 if (pwrctrl->wake_src_cust == 0) 223 mask = pwrctrl->wake_src; 224 else 225 mask = pwrctrl->wake_src_cust; 226 227 if (pwrctrl->syspwreq_mask) 228 mask &= ~WAKE_SRC_SYSPWREQ; 229 230 mmio_write_32(SPM_SLEEP_WAKEUP_EVENT_MASK, ~mask); 231 mmio_write_32(SPM_SLEEP_ISR_MASK, 0xfe04); 232 } 233 234 void spm_get_wakeup_status(struct wake_status *wakesta) 235 { 236 wakesta->assert_pc = mmio_read_32(SPM_PCM_REG_DATA_INI); 237 wakesta->r12 = mmio_read_32(SPM_PCM_REG12_DATA); 238 wakesta->raw_sta = mmio_read_32(SPM_SLEEP_ISR_RAW_STA); 239 wakesta->wake_misc = mmio_read_32(SPM_SLEEP_WAKEUP_MISC); 240 wakesta->timer_out = mmio_read_32(SPM_PCM_TIMER_OUT); 241 wakesta->r13 = mmio_read_32(SPM_PCM_REG13_DATA); 242 wakesta->idle_sta = mmio_read_32(SPM_SLEEP_SUBSYS_IDLE_STA); 243 wakesta->debug_flag = mmio_read_32(SPM_PCM_PASR_DPD_3); 244 wakesta->event_reg = mmio_read_32(SPM_PCM_EVENT_REG_STA); 245 wakesta->isr = mmio_read_32(SPM_SLEEP_ISR_STATUS); 246 } 247 248 void spm_init_event_vector(const struct pcm_desc *pcmdesc) 249 { 250 /* init event vector register */ 251 mmio_write_32(SPM_PCM_EVENT_VECTOR0, pcmdesc->vec0); 252 mmio_write_32(SPM_PCM_EVENT_VECTOR1, pcmdesc->vec1); 253 mmio_write_32(SPM_PCM_EVENT_VECTOR2, pcmdesc->vec2); 254 mmio_write_32(SPM_PCM_EVENT_VECTOR3, pcmdesc->vec3); 255 mmio_write_32(SPM_PCM_EVENT_VECTOR4, pcmdesc->vec4); 256 mmio_write_32(SPM_PCM_EVENT_VECTOR5, pcmdesc->vec5); 257 mmio_write_32(SPM_PCM_EVENT_VECTOR6, pcmdesc->vec6); 258 mmio_write_32(SPM_PCM_EVENT_VECTOR7, pcmdesc->vec7); 259 260 /* event vector will be enabled by PCM itself */ 261 } 262 263 void spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc) 264 { 265 unsigned int ptr = 0, len, con0; 266 267 ptr = (unsigned int)(unsigned long)(pcmdesc->base); 268 len = pcmdesc->size - 1; 269 if (mmio_read_32(SPM_PCM_IM_PTR) != ptr || 270 mmio_read_32(SPM_PCM_IM_LEN) != len || 271 pcmdesc->sess > 2) { 272 mmio_write_32(SPM_PCM_IM_PTR, ptr); 273 mmio_write_32(SPM_PCM_IM_LEN, len); 274 } else { 275 mmio_setbits_32(SPM_PCM_CON1, CON1_CFG_KEY | CON1_IM_SLAVE); 276 } 277 278 /* kick IM to fetch (only toggle IM_KICK) */ 279 con0 = mmio_read_32(SPM_PCM_CON0) & ~(CON0_IM_KICK | CON0_PCM_KICK); 280 mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY | CON0_IM_KICK); 281 mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY); 282 283 /* kick IM to fetch (only toggle PCM_KICK) */ 284 con0 = mmio_read_32(SPM_PCM_CON0) & ~(CON0_IM_KICK | CON0_PCM_KICK); 285 mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY | CON0_PCM_KICK); 286 mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY); 287 } 288 289 void spm_set_sysclk_settle(void) 290 { 291 mmio_write_32(SPM_CLK_SETTLE, SPM_SYSCLK_SETTLE); 292 293 INFO("settle = %u\n", mmio_read_32(SPM_CLK_SETTLE)); 294 } 295 296 void spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl) 297 { 298 unsigned int con1; 299 300 con1 = mmio_read_32(SPM_PCM_CON1) & 301 ~(CON1_PCM_WDT_WAKE_MODE | CON1_PCM_WDT_EN); 302 303 mmio_write_32(SPM_PCM_CON1, CON1_CFG_KEY | con1); 304 305 if (mmio_read_32(SPM_PCM_TIMER_VAL) > PCM_TIMER_MAX) 306 mmio_write_32(SPM_PCM_TIMER_VAL, PCM_TIMER_MAX); 307 308 mmio_write_32(SPM_PCM_WDT_TIMER_VAL, 309 mmio_read_32(SPM_PCM_TIMER_VAL) + PCM_WDT_TIMEOUT); 310 311 mmio_write_32(SPM_PCM_CON1, con1 | CON1_CFG_KEY | CON1_PCM_WDT_EN); 312 mmio_write_32(SPM_PCM_PASR_DPD_0, 0); 313 314 mmio_write_32(SPM_PCM_MAS_PAUSE_MASK, 0xffffffff); 315 mmio_write_32(SPM_PCM_REG_DATA_INI, 0); 316 mmio_clrbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR); 317 318 mmio_write_32(SPM_PCM_FLAGS, pwrctrl->pcm_flags); 319 320 mmio_clrsetbits_32(SPM_CLK_CON, CC_LOCK_INFRA_DCM, 321 (pwrctrl->infra_dcm_lock ? CC_LOCK_INFRA_DCM : 0)); 322 323 mmio_write_32(SPM_PCM_PWR_IO_EN, 324 (pwrctrl->r0_ctrl_en ? PCM_PWRIO_EN_R0 : 0) | 325 (pwrctrl->r7_ctrl_en ? PCM_PWRIO_EN_R7 : 0)); 326 } 327 328 void spm_clean_after_wakeup(void) 329 { 330 mmio_clrsetbits_32(SPM_PCM_CON1, CON1_PCM_WDT_EN, CON1_CFG_KEY); 331 332 mmio_write_32(SPM_PCM_PWR_IO_EN, 0); 333 mmio_write_32(SPM_SLEEP_CPU_WAKEUP_EVENT, 0); 334 mmio_clrsetbits_32(SPM_PCM_CON1, CON1_PCM_TIMER_EN, CON1_CFG_KEY); 335 336 mmio_write_32(SPM_SLEEP_WAKEUP_EVENT_MASK, ~0); 337 mmio_write_32(SPM_SLEEP_ISR_MASK, 0xFF0C); 338 mmio_write_32(SPM_SLEEP_ISR_STATUS, 0xC); 339 mmio_write_32(SPM_PCM_SW_INT_CLEAR, 0xFF); 340 } 341 342 enum wake_reason_t spm_output_wake_reason(struct wake_status *wakesta) 343 { 344 enum wake_reason_t wr; 345 int i; 346 347 wr = WR_UNKNOWN; 348 349 if (wakesta->assert_pc != 0) { 350 ERROR("PCM ASSERT AT %u, r12=0x%x, r13=0x%x, debug_flag=0x%x\n", 351 wakesta->assert_pc, wakesta->r12, wakesta->r13, 352 wakesta->debug_flag); 353 return WR_PCM_ASSERT; 354 } 355 356 if (wakesta->r12 & WAKE_SRC_SPM_MERGE) { 357 if (wakesta->wake_misc & WAKE_MISC_PCM_TIMER) 358 wr = WR_PCM_TIMER; 359 if (wakesta->wake_misc & WAKE_MISC_CPU_WAKE) 360 wr = WR_WAKE_SRC; 361 } 362 363 for (i = 1; i < 32; i++) { 364 if (wakesta->r12 & (1U << i)) 365 wr = WR_WAKE_SRC; 366 } 367 368 if ((wakesta->event_reg & 0x100000) == 0) { 369 INFO("pcm sleep abort!\n"); 370 wr = WR_PCM_ABORT; 371 } 372 373 INFO("timer_out = %u, r12 = 0x%x, r13 = 0x%x, debug_flag = 0x%x\n", 374 wakesta->timer_out, wakesta->r12, wakesta->r13, 375 wakesta->debug_flag); 376 377 INFO("raw_sta = 0x%x, idle_sta = 0x%x, event_reg = 0x%x, isr = 0x%x\n", 378 wakesta->raw_sta, wakesta->idle_sta, wakesta->event_reg, 379 wakesta->isr); 380 381 INFO("dormant state = %d\n", spm_dormant_sta); 382 return wr; 383 } 384 385 void spm_boot_init(void) 386 { 387 /* Only CPU0 is online during boot, initialize cpu online reserve bit */ 388 mmio_write_32(SPM_PCM_RESERVE, 0xFE); 389 mmio_clrbits_32(AP_PLL_CON3, 0xFFFFF); 390 mmio_clrbits_32(AP_PLL_CON4, 0xF); 391 spm_lock_init(); 392 spm_register_init(); 393 } 394