xref: /rk3399_ARM-atf/plat/mediatek/mt8173/drivers/rtc/rtc.h (revision c3cf06f1a3a9b9ee8ac7a0ae505f95c45f7dca84)
17d116dccSCC Ma /*
27d116dccSCC Ma  * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
37d116dccSCC Ma  *
482cb2c1aSdp-arm  * SPDX-License-Identifier: BSD-3-Clause
57d116dccSCC Ma  */
67d116dccSCC Ma 
7*c3cf06f1SAntonio Nino Diaz #ifndef RTC_H
8*c3cf06f1SAntonio Nino Diaz #define RTC_H
97d116dccSCC Ma 
107d116dccSCC Ma /* RTC registers */
117d116dccSCC Ma enum {
127d116dccSCC Ma 	RTC_BBPU = 0xE000,
137d116dccSCC Ma 	RTC_IRQ_STA = 0xE002,
147d116dccSCC Ma 	RTC_IRQ_EN = 0xE004,
157d116dccSCC Ma 	RTC_CII_EN = 0xE006
167d116dccSCC Ma };
177d116dccSCC Ma 
187d116dccSCC Ma enum {
197d116dccSCC Ma 	RTC_OSC32CON = 0xE026,
207d116dccSCC Ma 	RTC_CON = 0xE03E,
217d116dccSCC Ma 	RTC_WRTGR = 0xE03C
227d116dccSCC Ma };
237d116dccSCC Ma 
247d116dccSCC Ma enum {
257d116dccSCC Ma 	RTC_PDN1 = 0xE02C,
267d116dccSCC Ma 	RTC_PDN2 = 0xE02E,
277d116dccSCC Ma 	RTC_SPAR0 = 0xE030,
287d116dccSCC Ma 	RTC_SPAR1 = 0xE032,
297d116dccSCC Ma 	RTC_PROT = 0xE036,
307d116dccSCC Ma 	RTC_DIFF = 0xE038,
317d116dccSCC Ma 	RTC_CALI = 0xE03A
327d116dccSCC Ma };
337d116dccSCC Ma 
347d116dccSCC Ma enum {
357d116dccSCC Ma 	RTC_PROT_UNLOCK1 = 0x586A,
367d116dccSCC Ma 	RTC_PROT_UNLOCK2 = 0x9136
377d116dccSCC Ma };
387d116dccSCC Ma 
397d116dccSCC Ma enum {
407d116dccSCC Ma 	RTC_BBPU_PWREN	= 1U << 0,
417d116dccSCC Ma 	RTC_BBPU_BBPU	= 1U << 2,
427d116dccSCC Ma 	RTC_BBPU_AUTO	= 1U << 3,
437d116dccSCC Ma 	RTC_BBPU_CLRPKY	= 1U << 4,
447d116dccSCC Ma 	RTC_BBPU_RELOAD	= 1U << 5,
457d116dccSCC Ma 	RTC_BBPU_CBUSY	= 1U << 6
467d116dccSCC Ma };
477d116dccSCC Ma 
487d116dccSCC Ma enum {
497d116dccSCC Ma 	RTC_BBPU_KEY	= 0x43 << 8
507d116dccSCC Ma };
517d116dccSCC Ma 
527d116dccSCC Ma void rtc_bbpu_power_down(void);
537d116dccSCC Ma 
54*c3cf06f1SAntonio Nino Diaz #endif /* RTC_H */
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