1*7d116dccSCC Ma /* 2*7d116dccSCC Ma * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3*7d116dccSCC Ma * 4*7d116dccSCC Ma * Redistribution and use in source and binary forms, with or without 5*7d116dccSCC Ma * modification, are permitted provided that the following conditions are met: 6*7d116dccSCC Ma * 7*7d116dccSCC Ma * Redistributions of source code must retain the above copyright notice, this 8*7d116dccSCC Ma * list of conditions and the following disclaimer. 9*7d116dccSCC Ma * 10*7d116dccSCC Ma * Redistributions in binary form must reproduce the above copyright notice, 11*7d116dccSCC Ma * this list of conditions and the following disclaimer in the documentation 12*7d116dccSCC Ma * and/or other materials provided with the distribution. 13*7d116dccSCC Ma * 14*7d116dccSCC Ma * Neither the name of ARM nor the names of its contributors may be used 15*7d116dccSCC Ma * to endorse or promote products derived from this software without specific 16*7d116dccSCC Ma * prior written permission. 17*7d116dccSCC Ma * 18*7d116dccSCC Ma * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*7d116dccSCC Ma * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*7d116dccSCC Ma * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*7d116dccSCC Ma * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*7d116dccSCC Ma * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*7d116dccSCC Ma * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*7d116dccSCC Ma * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*7d116dccSCC Ma * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*7d116dccSCC Ma * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*7d116dccSCC Ma * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*7d116dccSCC Ma * POSSIBILITY OF SUCH DAMAGE. 29*7d116dccSCC Ma */ 30*7d116dccSCC Ma #include <assert.h> 31*7d116dccSCC Ma #include <debug.h> 32*7d116dccSCC Ma #include <delay_timer.h> 33*7d116dccSCC Ma #include <mt8173_def.h> 34*7d116dccSCC Ma #include <pmic_wrap_init.h> 35*7d116dccSCC Ma #include <rtc.h> 36*7d116dccSCC Ma 37*7d116dccSCC Ma /* RTC busy status polling interval and retry count */ 38*7d116dccSCC Ma enum { 39*7d116dccSCC Ma RTC_WRTGR_POLLING_DELAY_MS = 10, 40*7d116dccSCC Ma RTC_WRTGR_POLLING_CNT = 100 41*7d116dccSCC Ma }; 42*7d116dccSCC Ma 43*7d116dccSCC Ma static uint16_t RTC_Read(uint32_t addr) 44*7d116dccSCC Ma { 45*7d116dccSCC Ma uint32_t rdata = 0; 46*7d116dccSCC Ma 47*7d116dccSCC Ma pwrap_read((uint32_t)addr, &rdata); 48*7d116dccSCC Ma return (uint16_t)rdata; 49*7d116dccSCC Ma } 50*7d116dccSCC Ma 51*7d116dccSCC Ma static void RTC_Write(uint32_t addr, uint16_t data) 52*7d116dccSCC Ma { 53*7d116dccSCC Ma pwrap_write((uint32_t)addr, (uint32_t)data); 54*7d116dccSCC Ma } 55*7d116dccSCC Ma 56*7d116dccSCC Ma static inline int32_t rtc_busy_wait(void) 57*7d116dccSCC Ma { 58*7d116dccSCC Ma uint64_t retry = RTC_WRTGR_POLLING_CNT; 59*7d116dccSCC Ma 60*7d116dccSCC Ma do { 61*7d116dccSCC Ma mdelay(RTC_WRTGR_POLLING_DELAY_MS); 62*7d116dccSCC Ma if (!(RTC_Read(RTC_BBPU) & RTC_BBPU_CBUSY)) 63*7d116dccSCC Ma return 1; 64*7d116dccSCC Ma retry--; 65*7d116dccSCC Ma } while (retry); 66*7d116dccSCC Ma 67*7d116dccSCC Ma ERROR("[RTC] rtc cbusy time out!\n"); 68*7d116dccSCC Ma return 0; 69*7d116dccSCC Ma } 70*7d116dccSCC Ma 71*7d116dccSCC Ma static int32_t Write_trigger(void) 72*7d116dccSCC Ma { 73*7d116dccSCC Ma RTC_Write(RTC_WRTGR, 1); 74*7d116dccSCC Ma return rtc_busy_wait(); 75*7d116dccSCC Ma } 76*7d116dccSCC Ma 77*7d116dccSCC Ma static int32_t Writeif_unlock(void) 78*7d116dccSCC Ma { 79*7d116dccSCC Ma RTC_Write(RTC_PROT, RTC_PROT_UNLOCK1); 80*7d116dccSCC Ma if (!Write_trigger()) 81*7d116dccSCC Ma return 0; 82*7d116dccSCC Ma RTC_Write(RTC_PROT, RTC_PROT_UNLOCK2); 83*7d116dccSCC Ma if (!Write_trigger()) 84*7d116dccSCC Ma return 0; 85*7d116dccSCC Ma 86*7d116dccSCC Ma return 1; 87*7d116dccSCC Ma } 88*7d116dccSCC Ma 89*7d116dccSCC Ma void rtc_bbpu_power_down(void) 90*7d116dccSCC Ma { 91*7d116dccSCC Ma uint16_t bbpu; 92*7d116dccSCC Ma 93*7d116dccSCC Ma /* pull PWRBB low */ 94*7d116dccSCC Ma bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_PWREN; 95*7d116dccSCC Ma if (Writeif_unlock()) { 96*7d116dccSCC Ma RTC_Write(RTC_BBPU, bbpu); 97*7d116dccSCC Ma if (!Write_trigger()) 98*7d116dccSCC Ma assert(1); 99*7d116dccSCC Ma } else { 100*7d116dccSCC Ma assert(1); 101*7d116dccSCC Ma } 102*7d116dccSCC Ma } 103