1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #include <mmio.h> 31 #include <mt8173_def.h> 32 #include <mtcmos.h> 33 #include <spm.h> 34 35 enum { 36 SRAM_ISOINT_B = 1U << 6, 37 SRAM_CKISO = 1U << 5, 38 PWR_CLK_DIS = 1U << 4, 39 PWR_ON_2ND = 1U << 3, 40 PWR_ON = 1U << 2, 41 PWR_ISO = 1U << 1, 42 PWR_RST_B = 1U << 0 43 }; 44 45 enum { 46 L1_PDN_ACK = 1U << 8, 47 L1_PDN = 1U << 0 48 }; 49 50 enum { 51 LITTLE_CPU3 = 1U << 12, 52 LITTLE_CPU2 = 1U << 11, 53 LITTLE_CPU1 = 1U << 10, 54 }; 55 56 enum { 57 SRAM_PDN = 0xf << 8, 58 DIS_SRAM_ACK = 0x1 << 12, 59 AUD_SRAM_ACK = 0xf << 12, 60 }; 61 62 enum { 63 DIS_PWR_STA_MASK = 0x1 << 3, 64 AUD_PWR_STA_MASK = 0x1 << 24, 65 }; 66 67 static void mtcmos_ctrl_little_off(unsigned int linear_id) 68 { 69 uint32_t reg_pwr_con; 70 uint32_t reg_l1_pdn; 71 uint32_t bit_cpu; 72 73 switch (linear_id) { 74 case 1: 75 reg_pwr_con = SPM_CA7_CPU1_PWR_CON; 76 reg_l1_pdn = SPM_CA7_CPU1_L1_PDN; 77 bit_cpu = LITTLE_CPU1; 78 break; 79 case 2: 80 reg_pwr_con = SPM_CA7_CPU2_PWR_CON; 81 reg_l1_pdn = SPM_CA7_CPU2_L1_PDN; 82 bit_cpu = LITTLE_CPU2; 83 break; 84 case 3: 85 reg_pwr_con = SPM_CA7_CPU3_PWR_CON; 86 reg_l1_pdn = SPM_CA7_CPU3_L1_PDN; 87 bit_cpu = LITTLE_CPU3; 88 break; 89 default: 90 /* should never come to here */ 91 return; 92 } 93 94 /* enable register control */ 95 mmio_write_32(SPM_POWERON_CONFIG_SET, 96 (SPM_PROJECT_CODE << 16) | (1U << 0)); 97 98 mmio_setbits_32(reg_pwr_con, PWR_ISO); 99 mmio_setbits_32(reg_pwr_con, SRAM_CKISO); 100 mmio_clrbits_32(reg_pwr_con, SRAM_ISOINT_B); 101 mmio_setbits_32(reg_l1_pdn, L1_PDN); 102 103 while (!(mmio_read_32(reg_l1_pdn) & L1_PDN_ACK)) 104 continue; 105 106 mmio_clrbits_32(reg_pwr_con, PWR_RST_B); 107 mmio_setbits_32(reg_pwr_con, PWR_CLK_DIS); 108 mmio_clrbits_32(reg_pwr_con, PWR_ON); 109 mmio_clrbits_32(reg_pwr_con, PWR_ON_2ND); 110 111 while ((mmio_read_32(SPM_PWR_STATUS) & bit_cpu) || 112 (mmio_read_32(SPM_PWR_STATUS_2ND) & bit_cpu)) 113 continue; 114 } 115 116 void mtcmos_little_cpu_off(void) 117 { 118 /* turn off little cpu 1 - 3 */ 119 mtcmos_ctrl_little_off(1); 120 mtcmos_ctrl_little_off(2); 121 mtcmos_ctrl_little_off(3); 122 } 123