1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #include <mmio.h> 31 #include <mt8173_def.h> 32 #include <debug.h> 33 #include <mtcmos.h> 34 #include <spm.h> 35 #include <spm_mcdi.h> 36 #include <delay_timer.h> 37 38 enum { 39 SRAM_ISOINT_B = 1U << 6, 40 SRAM_CKISO = 1U << 5, 41 PWR_CLK_DIS = 1U << 4, 42 PWR_ON_2ND = 1U << 3, 43 PWR_ON = 1U << 2, 44 PWR_ISO = 1U << 1, 45 PWR_RST_B = 1U << 0 46 }; 47 48 enum { 49 L1_PDN_ACK = 1U << 8, 50 L1_PDN = 1U << 0 51 }; 52 53 enum { 54 LITTLE_CPU3 = 1U << 12, 55 LITTLE_CPU2 = 1U << 11, 56 LITTLE_CPU1 = 1U << 10, 57 }; 58 59 enum { 60 SRAM_PDN = 0xf << 8, 61 DIS_SRAM_ACK = 0x1 << 12, 62 AUD_SRAM_ACK = 0xf << 12, 63 }; 64 65 enum { 66 DIS_PWR_STA_MASK = 0x1 << 3, 67 AUD_PWR_STA_MASK = 0x1 << 24, 68 }; 69 70 #define SPM_VDE_PWR_CON 0x0210 71 #define SPM_MFG_PWR_CON 0x0214 72 #define SPM_VEN_PWR_CON 0x0230 73 #define SPM_ISP_PWR_CON 0x0238 74 #define SPM_DIS_PWR_CON 0x023c 75 #define SPM_VEN2_PWR_CON 0x0298 76 #define SPM_AUDIO_PWR_CON 0x029c 77 #define SPM_MFG_2D_PWR_CON 0x02c0 78 #define SPM_MFG_ASYNC_PWR_CON 0x02c4 79 #define SPM_USB_PWR_CON 0x02cc 80 81 #define MTCMOS_CTRL_SUCCESS 0 82 #define MTCMOS_CTRL_ERROR -1 83 84 #define MTCMOS_CTRL_EN (0x1 << 18) 85 86 #define VDE_PWR_ON 0 87 #define VEN_PWR_ON 1 88 #define ISP_PWR_ON 2 89 #define DIS_PWR_ON 3 90 #define VEN2_PWR_ON 4 91 #define AUDIO_PWR_ON 5 92 #define MFG_ASYNC_PWR_ON 6 93 #define MFG_2D_PWR_ON 7 94 #define MFG_PWR_ON 8 95 #define USB_PWR_ON 9 96 97 #define VDE_PWR_OFF 10 98 #define VEN_PWR_OFF 11 99 #define ISP_PWR_OFF 12 100 #define DIS_PWR_OFF 13 101 #define VEN2_PWR_OFF 14 102 #define AUDIO_PWR_OFF 15 103 #define MFG_ASYNC_PWR_OFF 16 104 #define MFG_2D_PWR_OFF 17 105 #define MFG_PWR_OFF 18 106 #define USB_PWR_OFF 19 107 108 #define VDE_PWR_CON_PWR_STA 7 109 #define VEN_PWR_CON_PWR_STA 21 110 #define ISP_PWR_CON_PWR_STA 5 111 #define DIS_PWR_CON_PWR_STA 3 112 #define VEN2_PWR_CON_PWR_STA 20 113 #define AUDIO_PWR_CON_PWR_STA 24 114 #define MFG_ASYNC_PWR_CON_PWR_STA 23 115 #define MFG_2D_PWR_CON_PWR_STA 22 116 #define MFG_PWR_CON_PWR_STA 4 117 #define USB_PWR_CON_PWR_STA 25 118 119 /* 120 * Timeout if the ack is not signled after 1 second. 121 * According to designer, one mtcmos operation should be done 122 * around 10us. 123 */ 124 #define MTCMOS_ACK_POLLING_MAX_COUNT 10000 125 #define MTCMOS_ACK_POLLING_INTERVAL 10 126 127 static void mtcmos_ctrl_little_off(unsigned int linear_id) 128 { 129 uint32_t reg_pwr_con; 130 uint32_t reg_l1_pdn; 131 uint32_t bit_cpu; 132 133 switch (linear_id) { 134 case 1: 135 reg_pwr_con = SPM_CA7_CPU1_PWR_CON; 136 reg_l1_pdn = SPM_CA7_CPU1_L1_PDN; 137 bit_cpu = LITTLE_CPU1; 138 break; 139 case 2: 140 reg_pwr_con = SPM_CA7_CPU2_PWR_CON; 141 reg_l1_pdn = SPM_CA7_CPU2_L1_PDN; 142 bit_cpu = LITTLE_CPU2; 143 break; 144 case 3: 145 reg_pwr_con = SPM_CA7_CPU3_PWR_CON; 146 reg_l1_pdn = SPM_CA7_CPU3_L1_PDN; 147 bit_cpu = LITTLE_CPU3; 148 break; 149 default: 150 /* should never come to here */ 151 return; 152 } 153 154 /* enable register control */ 155 mmio_write_32(SPM_POWERON_CONFIG_SET, 156 (SPM_PROJECT_CODE << 16) | (1U << 0)); 157 158 mmio_setbits_32(reg_pwr_con, PWR_ISO); 159 mmio_setbits_32(reg_pwr_con, SRAM_CKISO); 160 mmio_clrbits_32(reg_pwr_con, SRAM_ISOINT_B); 161 mmio_setbits_32(reg_l1_pdn, L1_PDN); 162 163 while (!(mmio_read_32(reg_l1_pdn) & L1_PDN_ACK)) 164 continue; 165 166 mmio_clrbits_32(reg_pwr_con, PWR_RST_B); 167 mmio_setbits_32(reg_pwr_con, PWR_CLK_DIS); 168 mmio_clrbits_32(reg_pwr_con, PWR_ON); 169 mmio_clrbits_32(reg_pwr_con, PWR_ON_2ND); 170 171 while ((mmio_read_32(SPM_PWR_STATUS) & bit_cpu) || 172 (mmio_read_32(SPM_PWR_STATUS_2ND) & bit_cpu)) 173 continue; 174 } 175 176 void mtcmos_little_cpu_off(void) 177 { 178 /* turn off little cpu 1 - 3 */ 179 mtcmos_ctrl_little_off(1); 180 mtcmos_ctrl_little_off(2); 181 mtcmos_ctrl_little_off(3); 182 } 183 184 uint32_t wait_mtcmos_ack(uint32_t on, uint32_t pwr_ctrl, uint32_t spm_pwr_sta) 185 { 186 int i = 0; 187 uint32_t cmp, pwr_sta, pwr_sta_2nd; 188 189 while (1) { 190 cmp = mmio_read_32(SPM_PCM_PASR_DPD_3) & pwr_ctrl; 191 pwr_sta = (mmio_read_32(SPM_PWR_STATUS) >> spm_pwr_sta) & 1; 192 pwr_sta_2nd = 193 (mmio_read_32(SPM_PWR_STATUS_2ND) >> spm_pwr_sta) & 1; 194 if (cmp && (pwr_sta == on) && (pwr_sta_2nd == on)) { 195 mmio_write_32(SPM_PCM_RESERVE2, 0); 196 return MTCMOS_CTRL_SUCCESS; 197 } 198 udelay(MTCMOS_ACK_POLLING_INTERVAL); 199 i++; 200 if (i > MTCMOS_ACK_POLLING_MAX_COUNT) { 201 INFO("MTCMOS control failed(%d), SPM_PWR_STA(%d),\n" 202 "SPM_PCM_RESERVE=0x%x,SPM_PCM_RESERVE2=0x%x,\n" 203 "SPM_PWR_STATUS=0x%x,SPM_PWR_STATUS_2ND=0x%x\n" 204 "SPM_PCM_PASR_DPD_3 = 0x%x\n", 205 on, spm_pwr_sta, mmio_read_32(SPM_PCM_RESERVE), 206 mmio_read_32(SPM_PCM_RESERVE2), 207 mmio_read_32(SPM_PWR_STATUS), 208 mmio_read_32(SPM_PWR_STATUS_2ND), 209 mmio_read_32(SPM_PCM_PASR_DPD_3)); 210 mmio_write_32(SPM_PCM_RESERVE2, 0); 211 return MTCMOS_CTRL_ERROR; 212 } 213 } 214 } 215 216 uint32_t mtcmos_non_cpu_ctrl(uint32_t on, uint32_t mtcmos_num) 217 { 218 uint32_t ret = MTCMOS_CTRL_SUCCESS; 219 uint32_t power_on; 220 uint32_t power_off; 221 uint32_t power_ctrl; 222 uint32_t power_status; 223 224 spm_lock_get(); 225 spm_mcdi_prepare_for_mtcmos(); 226 mmio_setbits_32(SPM_PCM_RESERVE, MTCMOS_CTRL_EN); 227 228 switch (mtcmos_num) { 229 case SPM_VDE_PWR_CON: 230 power_on = VDE_PWR_ON; 231 power_off = VDE_PWR_OFF; 232 power_status = VDE_PWR_CON_PWR_STA; 233 break; 234 case SPM_MFG_PWR_CON: 235 power_on = MFG_PWR_ON; 236 power_off = MFG_PWR_OFF; 237 power_status = MFG_PWR_CON_PWR_STA; 238 break; 239 case SPM_VEN_PWR_CON: 240 power_on = VEN_PWR_ON; 241 power_off = VEN_PWR_OFF; 242 power_status = VEN_PWR_CON_PWR_STA; 243 break; 244 case SPM_ISP_PWR_CON: 245 power_on = ISP_PWR_ON; 246 power_off = ISP_PWR_OFF; 247 power_status = ISP_PWR_CON_PWR_STA; 248 break; 249 case SPM_DIS_PWR_CON: 250 power_on = DIS_PWR_ON; 251 power_off = DIS_PWR_OFF; 252 power_status = DIS_PWR_CON_PWR_STA; 253 break; 254 case SPM_VEN2_PWR_CON: 255 power_on = VEN2_PWR_ON; 256 power_off = VEN2_PWR_OFF; 257 power_status = VEN2_PWR_CON_PWR_STA; 258 break; 259 case SPM_AUDIO_PWR_CON: 260 power_on = AUDIO_PWR_ON; 261 power_off = AUDIO_PWR_OFF; 262 power_status = AUDIO_PWR_CON_PWR_STA; 263 break; 264 case SPM_MFG_2D_PWR_CON: 265 power_on = MFG_2D_PWR_ON; 266 power_off = MFG_2D_PWR_OFF; 267 power_status = MFG_2D_PWR_CON_PWR_STA; 268 break; 269 case SPM_MFG_ASYNC_PWR_CON: 270 power_on = MFG_ASYNC_PWR_ON; 271 power_off = MFG_ASYNC_PWR_OFF; 272 power_status = MFG_ASYNC_PWR_CON_PWR_STA; 273 break; 274 case SPM_USB_PWR_CON: 275 power_on = USB_PWR_ON; 276 power_off = USB_PWR_OFF; 277 power_status = USB_PWR_CON_PWR_STA; 278 break; 279 default: 280 ret = MTCMOS_CTRL_ERROR; 281 INFO("No mapping MTCMOS(%d), ret = %d\n", mtcmos_num, ret); 282 break; 283 } 284 if (ret == MTCMOS_CTRL_SUCCESS) { 285 power_ctrl = on ? (1 << power_on) : (1 << power_off); 286 mmio_setbits_32(SPM_PCM_RESERVE2, power_ctrl); 287 ret = wait_mtcmos_ack(on, power_ctrl, power_status); 288 VERBOSE("0x%x(%d), PWR_STATUS(0x%x), ret(%d)\n", 289 power_ctrl, on, mmio_read_32(SPM_PWR_STATUS), ret); 290 } 291 292 mmio_clrbits_32(SPM_PCM_RESERVE, MTCMOS_CTRL_EN); 293 spm_lock_release(); 294 295 return ret; 296 } 297